DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 30 June 2026 have been fully considered but they are not persuasive. Applicant argues that Bao combined with Sung fails to disclose, “first epitaxial source/drain regions extending from above the first end portions to below the bottom most nanosheet of the first nanosheets such that the first epitaxial source/drain regions are in contact with the first end portions and the bottom most nanosheet,” recited in amended claim 1. This is unpersuasive, as both Bao and the combination of Sung and Bao teach this limitation. Viewing the first nanosheets of Bao, as the nanosheets which contact the source/drain region, the first epitaxial source/drain regions are in contact with the first end portions and the bottom most nanosheet of the first nanosheets. Additionally, Bao is not relied upon for the teaching of forming a dielectric layer below the source/drain regions, which is a separate teaching, but for the teaching of end portions. Therefore, the combination of Sung and Bao teaches the above limitation and specifically does not fail to teach, “the first epitaxial source/drain regions are in contact with the first end portions and the bottom most nanosheet”. Applicant also argues that Sung would not be modified in the manner suggested by the office action because Sung uses different elements, such as element 206 and extended spacers 265, to have a varied number of nanosheets in the transistors. This is unpersuasive, as the structure of Sung, such as lacking end portions intervening in the extended spacer 265, provides motivation to improve on the structure of Sung using the teaching of Bao. Bao teaches preserving end portions of the etched channel layers as an alternative method for reducing the number of upper nanosheets in a transistor for the benefit of providing a surface for epitaxial growth of the source/drain regions.
The prior drawing objection is withdrawn in view of amendments to the drawings. The prior specification objection is withdrawn in view of amendments to the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. (US 10170484 B1; hereinafter referred to as “Sung”) in view of Bao et al. (US PGPub 20180114833 A1; hereinafter referred to as “Bao”).
Re claim 1: Sung teaches a semiconductor structure (FIG. 14A; col. 1: line 43-64; col. 15: line 51-60) comprising: a first transistor (FIG. 14E: el. 250c; col. 15: line 65 – col. 16: line 8) having first nanosheets as first channel regions (FIG. 14E: el. 244c; col. 16: line 46-67), a second transistor (FIG. 14D: el. 250b; col. 15: line 65 – col. 16: line 8) having second nanosheets as second channel regions (FIG. 14D: el. 244; col. 16: line: 25-45|second nanosheets labelled 244b in specification but have the label 244 in figure 14D), and a third transistor (FIG. 14C: el. 250a; col. 15: line 65 – col. 16: line 8) having third nanosheets as third channel regions (FIG. 14C: el. 244a; col. 16: line: 9-24), the first, second, and third nanosheets being formed of a nanosheet material (col 13: line 57 - col. 14: line 16|nanosheets 244 formed of the material of the first semiconductor material 204), wherein the first nanosheets are fewer in number than the second nanosheets (FIG. 14E, 14D: el. 244c, 244; col. 16: line 50-55); first epitaxial source/drain regions (FIG. 14E: el. 241c; para. 40) in contact with the bottom most nanosheet (FIG. 14E: el. 241c, 244c); interlayer dielectric material (FIG. 14E: el. 232; para. 42) disposed on top of the first epitaxial source/drain regions (FIG. 14E: el. 241c, 232); and gate spacers (FIG. 14E: el. 261; para. 35) disposed on sidewalls of both the first epitaxial source/drain regions and the interlayer dielectric material (FIG. 14E: el. 261, 241, 232). Sung fails to teach first end portions formed of the nanosheet material between first inner spacers in the first transistor, the first end portions being opposite one another and discontinuous in the first transistor; wherein the first end portions are on a level different from a bottom most nanosheet of the first nanosheets; first epitaxial source/drain regions extending from above the first end portions to below the bottom most nanosheet of the first nanosheets such that the first epitaxial source/drain regions are in contact with the first end portions; and gate spacers disposed on top of the first inner spacers, disposed over the first end portions, wherein a stack is formed of the gate spacers and the first end portions with the first inner spacers intervening.
In a similar field of endeavor, Bao teaches first nanosheets (FIG. 7, as labelled below by examiner: el. 1st nanosheets; para. 39) and first end portions (FIG. 7, as labelled below by examiner: el. END PORTION; para. 39) formed of the nanosheet material between first inner spacers (FIG. 7, as labelled below by examiner: el. INNER SPACER) in the first transistor, the first end portions being opposite one another and discontinuous in the first transistor (FIG. 7; para. 39-40|end portions are formed by etching the nanosheet channel layer only in the region between horizontally spaced inner spacers so as to leave remaining end portions between vertically spaced inner spacers (horizontal/vertical directions as shown in FIG. 7); end portions are opposite one another, discontinuous, and formed of the nanosheet material); wherein the first end portions are on a level different from a bottom most nanosheet of the first nanosheets (FIG. 7, as labelled below by examiner: el. END PORTION, 1st nanosheets); first epitaxial source/drain regions (FIG. 7: el. 704; para. 39) extending from above the first end portions to below the bottom most nanosheet of the first nanosheets such that the first epitaxial source/drain regions are in contact with the first end portions and the bottom most nanosheet (FIG. 7, as labelled below by examiner: el. 704, END PORTION, 1st nanosheets). The combination of Bao and Sung teaches gate spacers disposed on top of the first inner spacers, disposed over the first end portions, wherein a stack is formed of the gate spacers and the first end portions with the first inner spacers intervening (Sung – annotated FIG. 14E, provided below|using the teaching of the end portions of Bao in the semiconductor structure of Sung would yield first inner spacers between first end portions and a stack of gate spacers disposed on top of first inner spacers and first end portions with the first inner spacers intervening between the first end portions). Bao also teaches a benefit of the first end portions is that they provide a surface for epitaxial growth of the source/drain regions (para. 39).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Sung and Bao, to enable using the inner spacers and end portions of Bao in the semiconductor structure of Sung, for the benefit of improving a growth characteristic of the source/drain regions by providing a surface for epitaxial growth and the benefit of increasing process uniformity for transistors with different numbers of nanosheet channels.
Re claim 2: The combination of Sung and Bao teaches the semiconductor structure of claim 1, wherein the second nanosheets are fewer in number than the third nanosheets (Sung - FIG. 14D, 14C: el. 244, 244a; col. 16: line: 25-45| second nanosheets labelled 244b in specification but have the label 244 in figure 14D).
Re claim 3: The combination of Sung and Bao teaches the semiconductor structure of claim 1, wherein the first end portions are in direct contact with the first epitaxial source/drain regions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION, 704; para. 39)(Sung – annotated FIG. 14E, provided above in Re claim 1 section: el. 1st end portion, 241c).
Re claim 4: The combination of Sung and Bao teaches the semiconductor structure of claim 1, wherein second end portions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION) are formed of the nanosheet material between second inner spacers (Bao - FIG. 7, as labelled above by examiner: el. INNER SPACER) in the second transistor, the second end portions being opposite one another and discontinuous in the second transistor (Bao - FIG. 7; para. 39-40|end portions are formed by etching the nanosheet channel layer only in the region between horizontally spaced inner spacers so as to leave remaining end portions between vertically spaced inner spacers (horizontal/vertical directions as shown in FIG. 7); end portions are opposite one another, discontinuous, and formed of the nanosheet material).
Re claim 5: The combination of Sung and Bao teaches the semiconductor structure of claim 4, wherein the second end portions are adjacent to epitaxial source/drain regions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION, 704; para. 39) and fewer in number than the first end portions (Bao teaches end portions formed from remaining portions of etched away nanosheets wherein the remaining portions are a pair of opposite and discontinuous end portions of the nanosheet layer (Bao - FIG. 7; para. 39-40); Sung teaches etching away fewer top nanosheets to form the second transistor (Sung – FIG. 4: el. 207a; col. 8: line 29-39; FIG. 6B: el. 212; col. 9: line 26-41) than are etched away to form the first transistor (Sung – FIG. 4: el. 207b; col. 8: line 29-39; FIG. 6B: el. 213; col. 9: line 26-41), and thus the combination of Sung and Bao teach fewer second end portions of the second transistor than first end portions of the first transistor).
Re claim 6: The combination of Sung and Bao teaches the semiconductor structure of claim 1, wherein epitaxial source/drain regions are substantially identical in the first, second, and third transistors (Sung - FIG. 14C, 14D, 14E: el. 241a, 241b, 241c; col. 12: line 19-40).
Re claim 7: The combination of Sung and Bao teaches the semiconductor structure of claim 1, wherein the first, second, and third transistors are formed to utilize different electrical current drive strengths (Sung - col. 2: line 27-30).
Re claim 8: Sung teaches a method (col. 2: line 27-30) comprising: providing a first transistor (FIG. 14E: el. 250c; col. 15: line 65 – col. 16: line 8) having first nanosheets as first channel regions (FIG. 14E: el. 244c; col. 16: line 46-67), a second transistor (FIG. 14D: el. 250b; col. 15: line 65 – col. 16: line 8) having second nanosheets as second channel regions (FIG. 14D: el. 244; col. 16: line: 25-45|second nanosheets labelled 244b in specification but have the label 244 in figure 14D), and a third transistor (FIG. 14C: el. 250a; col. 15: line 65 – col. 16: line 8) having third nanosheets as third channel regions (FIG. 14C: el. 244a; col. 16: line: 9-24), the first, second, and third nanosheets being formed of a nanosheet material (col 13: line 57 - col. 14: line 16|nanosheets 244 formed of the material of the first semiconductor material 204), wherein the first nanosheets are fewer in number than the second nanosheets (FIG. 14E, 14D: el. 244c, 244; col. 16: line 50-55); providing epitaxial source/drain regions (FIG. 14E: el. 241c; para. 40) in contact with the bottom most nanosheet (FIG. 14E: el. 241, 244c); disposing interlayer dielectric material (FIG. 14E: el. 232; para. 42) on top of the first epitaxial source/drain regions (FIG. 14E: el. 241c, 232); and providing gate spacers (FIG. 14E: el. 261; para. 35) disposed on sidewalls of both the first epitaxial source/drain regions and the interlayer dielectric material (FIG. 14E: el. 261, 241c, 232). Sung fails to teach providing first end portions formed of the nanosheet material between first inner spacers in the first transistor, the first end portions being opposite one another and discontinuous in the first transistor; wherein the first end portions are on a level different from a bottom most nanosheet of the first nanosheets; first epitaxial source/drain regions extending from above the first end portions to below the bottom most nanosheet of the first nanosheets such that the first epitaxial source/drain regions are in contact with the first end portions; and gate spacers disposed on top of the first inner spacers, disposed over the first end portions, wherein a stack is formed of the gate spacers and the first end portions with the first inner spacers intervening.
In a similar field of endeavor, Bao teaches providing first nanosheets (FIG. 7, as labelled below by examiner: el. 1st nanosheets; para. 39) and first end portions (FIG. 7, as labelled above by examiner: el. END PORTION; para. 39) formed of the nanosheet material between first inner spacers (FIG. 7, as labelled above by examiner: el. INNER SPACER) in the first transistor, the first end portions being opposite one another and discontinuous in the first transistor (FIG. 7; para. 39-40|end portions are formed by etching the nanosheet channel layer only in the region between horizontally spaced inner spacers so as to leave remaining end portions between vertically spaced inner spacers (horizontal/vertical directions as shown in FIG. 7); end portions are opposite one another, discontinuous, and formed of the nanosheet material); wherein the first end portions are on a level different from a bottom most nanosheet of the first nanosheets (FIG. 7, as labelled above by examiner: el. END PORTION, 1st nanosheets); providing epitaxial source/drain regions (FIG. 7: el. 704; para. 39) extending from above the first end portions to below the bottom most nanosheet of the first nanosheets such that the first epitaxial source/drain regions are in contact with the first end portions and the bottom most nanosheet (FIG. 7, as labelled above by examiner: el. 704, END PORTION, 1st nanosheets). The combination of Bao and Sung teaches providing gate spacers disposed on top of the first inner spacers, disposed over the first end portions, wherein a stack is formed of the gate spacers and the first end portions with the first inner spacers intervening (Sung – annotated FIG. 14E, provided above in Re claim 1 section| using the teaching of the end portions of Bao in the semiconductor structure of Sung would yield first inner spacers between first end portions and a stack of gate spacers disposed on top of both first inner spacers and first end portions with the first inner spacers intervening between the first end portions). Bao also teaches a benefit of the first end portions is that they provide a surface for epitaxial growth of the source/drain regions (para. 39).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Sung and Bao, to enable using the inner spacers and end portions of Bao in the method of providing transistors of Sung, for the benefit of improving a growth characteristic of the source/drain regions by providing a surface for epitaxial growth and the benefit of increasing process uniformity for transistors with different numbers of nanosheet channels.
Re claim 9: The combination of Sung and Bao teaches the method of claim 8, wherein the second nanosheets are fewer in number than the third nanosheets (Sung - FIG. 14D, 14C: el. 244, 244a; col. 16: line: 25-45| second nanosheets labelled 244b in specification but have the label 244 in figure 14D).
Re claim 10: The combination of Sung and Bao teaches the method of claim 8, wherein the first end portions are adjacent to the epitaxial source/drain regions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION, 704; para. 39) )(Sung – annotated FIG. 14E, provided above in Re claim 1 section: el. 1st end portion, 241c).
Re claim 11: The combination of Sung and Bao teaches the method of claim 8, wherein second end portions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION) are formed of the nanosheet material between second inner spacers (Bao - FIG. 7, as labelled above by examiner: el. INNER SPACER) in the second transistor, the second end portions being opposite one another and discontinuous in the second transistor (Bao - FIG. 7; para. 39-40|end portions are formed by etching the nanosheet channel layer only in the region between horizontally spaced inner spacers so as to leave remaining end portions between vertically spaced inner spacers (horizontal/vertical directions as shown in FIG. 7); end portions are opposite one another, discontinuous, and formed of the nanosheet material).
Re claim 12: The combination of Sung and Bao teaches the method of claim 11, wherein the second end portions are adjacent to epitaxial source/drain regions (Bao - FIG. 7, as labelled above by examiner: el. END PORTION, 704; para. 39) and fewer in number than the first end portions (Bao teaches end portions formed from remaining portions of etched away nanosheets wherein the remaining portions are a pair of opposite and discontinuous end portions of the nanosheet layer (Bao - FIG. 7; para. 39-40); Sung teaches etching away fewer top nanosheets to form the second transistor (Sung – FIG. 4: el. 207a; col. 8: line 29-39; FIG. 6B: el. 212; col. 9: line 26-41) than are etched away to form the first transistor (Sung – FIG. 4: el. 207b; col. 8: line 29-39; FIG. 6B: el. 213; col. 9: line 26-41), and thus the combination of Sung and Bao teach fewer second end portions of the second transistor than first end portions of the first transistor).
Re claim 13: The combination of Sung and Bao teaches the method of claim 8, wherein the epitaxial source/drain regions are substantially identical in the first, second, and third transistors (Sung - FIG. 14C, 14D, 14E: el. 241a, 241b, 241c; col. 12: line 19-40).
Re claim 14: The combination of Sung and Bao teaches the method of claim 8, wherein the first, second, and third transistors are formed to utilize different electrical current drive strengths (Sung - col. 2: line 27-30).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon teaches dielectric spacers and end portions in a manner that is similar to the relied upon prior art and the applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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