Prosecution Insights
Last updated: October 02, 2026
Application No. 18/449,941

METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)

Final Rejection §103
Filed
Aug 15, 2023
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+22.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao(USPGPUB DOCUMENT: 2023/0352396, hereinafter Hsiao) in view of Kunkel (USPATENT: 6282116, hereinafter Kunkel). Re claim 21 Hsiao discloses in Fig 18 a semiconductor device comprising:a first via(VIA1/VIA2/VIA3) that includes a metal insulator(164/168/172/175) metal (MIM) capacitor(160) surrounding the first via(VIA1/VIA2/VIA3), wherein the MIM capacitor includes a first outer metal plate(174/162) and a second outer metal plate(174/162), and a first insulator(164/168/172/175) and a second insulator(164/168/172/175) are located between the first outer metal plate(174/162) and the second outer metal plate(174/162), a second via(VIA1/VIA2/VIA3) that includes an inner metal plate(170) surrounding the second via(VIA1/VIA2/VIA3), Hsiao does not discloses wherein the MIM capacitor has a plus shaped profile when viewed from a top down perspective;a second via(VIA1/VIA2/VIA3) that includes an inner metal plate(170) surrounding the second via(VIA1/VIA2/VIA3), wherein the second plate has a plus shaped profile when viewed from the top down perspective, Kunkel discloses wherein the capacitor has a plus shaped profile when viewed from a top down perspective(31/41/34A/34B/34C/34D of Kunkel); It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kunkel to the teachings of Hsiao in order to permit more efficient packing [col1, lines 25-40, Kunkel]. In doing so, wherein the MIM capacitor has a plus shaped profile when viewed from a top down perspective(31/41/34A/34B/34C/34D of Kunkel); wherein the second plate has a plus shaped profile(31/41/34A/34B/34C/34D of Kunkel) when viewed from the top down perspective, Re claim 22 Hsiao and Kunkel disclose thesemiconductor device of claim 21, wherein the inner metal plate(170) is located between the first outer metal plate(174/162) and the second outer metal plate(174/162) in the location between the first via(VIA1/VIA2/VIA3) and the second via(VIA1/VIA2/VIA3), wherein the first insulator(164/168/172/175) is located between the first outer metal plate(174/162) and inner metal plate(170), and the second insulator(164/168/172/175) is located between inner metal plate(170) and the second outer metal plate(174/162). Re claim 23 Hsiao and Kunkel disclose thesemiconductor device of claim 21, wherein the inner plate is located around the second via(VIA1/VIA2/VIA3) is located on the same level as the first outer plate. Re claim 24 Hsiao and Kunkel disclose thesemiconductor device of claim 21, wherein openings in corners of the first outer metal plate(174/162) and the second outer metal plate(174/162) form the plus shaped profile around the first via(VIA1/VIA2/VIA3). Re claim 25 Hsiao and Kunkel disclose thesemiconductor device of claim 21, wherein openings in corners of the inner metal plate(170) forms the plus shaped profile around the second via(VIA1/VIA2/VIA3).Serial No. 18/449,941 Re claim 26 Hsiao and Kunkel disclose thesemiconductor device of claim 21, wherein the first insulator(164/168/172/175) is located beneath the inner metal plate(170) around the second via(VIA1/VIA2/VIA3). Re claim 27 Hsiao and Kunkel disclose thesemiconductor device of claim 26, wherein the second insulator(164/168/172/175) is located on top of the inner metal plate(170) around the second via(VIA1/VIA2/VIA3). Response to Arguments Applicant’s arguments with respect to claim(s) 21-27 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 15, 2023
Application Filed
Mar 25, 2026
Non-Final Rejection mailed — §103
Jun 22, 2026
Applicant Interview (Telephonic)
Jun 25, 2026
Response Filed
Sep 02, 2026
Examiner Interview Summary
Sep 10, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12721165
SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE
1y 0m to grant Granted Aug 25, 2026
Patent 12708031
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
3y 1m to grant Granted Aug 11, 2026
Patent 12702000
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 5m to grant Granted Aug 04, 2026
Patent 12701980
Layer-By-Layer Formation Of Through-Substrate Via
3y 4m to grant Granted Aug 04, 2026
Patent 12701999
SEMICONDUCTOR POWER MODULE
3y 0m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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