DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 11/17/2025, without traverse to prosecute the claims of Invention I, claims 1-6 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/15/2023 and 4/16/2024 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Schaeffer et al. (US 20200013859 A1).
Tamaso teaches a semiconductor device comprising:
a device region (101, page 8 par 4); and
a dicing region (102, page 8 par 2) surrounding the device region (101, FIG. 4),
the device region (101) including a first electrode (94, page 11 par 5),
a second electrode (98, page 11 par 5), and
a silicon carbide layer (10, page 12 par 2) having a first face (10a, FIG. 12) on a side of the first electrode (10 is on bottom surface of 12 which is on bottom surface of 94) and a second face (10b) on a side of the second electrode (98), at least a portion of the silicon carbide layer (10) provided between the first electrode (94) and the second electrode (98).
Tamaso does not teach the dicing region including the silicon carbide layer having the first face and the second face, wherein a first maximum distance from the second face to the first face of the device region in a normal direction of the second face is greater than a second maximum distance from the second face to the first face of the dicing region in the normal direction.
Schaeffer teaches the dicing region (660, FIG. 6B) [0139] including the silicon carbide layer (700) [0119] having the first face (701) and the second face (702), wherein a first maximum distance from the second face to the first face of the device region (650, FIG. 6C) [0122] in a normal direction of the second face is greater than a second maximum distance from the second face to the first face of the dicing region (660 FIG. 6B becomes 705 FIG. 6C) in the normal direction.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Schaeffer into the structure of Tamaso since Schaeffer teaches a semiconductor device with a silicon carbide substrate.
The ordinary artisan would have been motivated to modify Schaeffer in combination with Tamaso in the above manner for the motivation of making the dicing regions thinner than the device region since the dicing region will later e cut to form multiple chips. [0042] states, “From each device region a dicing process results in a single semiconductor die (“chip”), wherein the semiconductor die includes a block of semiconducting material, in or on which a given functional circuit is fabricated.”
Re Claim 2 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 1, but does not explicitly teach a difference between the first maximum distance and the second maximum distance is equal to or more than 0.5 µm.
Schaeffer teaches in [0153], “The splitting region 750 may have a thickness of at least 30 nm, typically at least 100 nm, and at most 1.5 μm, typically at most 500 nm.” FIG. 6C shows 750 is roughly 4x larger than d2-d1. If 750 is at least ~125nm, that would make d2-d1 at least ~500nm, .5 µm.
Annotated FIG. 6C shown below with distances labeled.
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461
779
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The ordinary artisan would have been motivated to modify Schaeffer in combination with in the above manner for the motivation of finding optimal distance difference between the die region and device region thicknesses.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal device region thickness vs dicing region thickness.
Re Claim 3 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 1, wherein the silicon carbide layer (Schaeffer, 700) in the device region (650) includes a first silicon carbide region (139) [0168] of a first conductive type (n+) and a second silicon carbide region (131, not mentioned in text, shown on FIG. 9A) provided on the first silicon carbide region (700), the second silicon carbide region having a first-conductive-type impurity concentration (n-) different from a first-conductive-type impurity concentration of the first silicon carbide region (139), and
the first silicon carbide region (139) is in contact with the first face of the dicing region (use 706 [0188] as dicing region, FIG. FIG. 9A-D).
Re Claim 6 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 1, wherein the device region (Tomaso, 101) further includes an insulating layer (93, page 11 last par) provided on the first electrode (94, FIG. 20),
and at least a portion of an outermost surface of the dicing region (102) on a side of the first face (10a) is the silicon carbide layer (10, FIG. 11).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Schaeffer et al. (US 20200013859 A1) and further in view of Hung et al. (US 20220223730 A1).
Re Claim 4 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 3, but does not teach the second silicon carbide region is an epitaxial growth layer formed on the first silicon carbide region.
Hung teaches the second silicon carbide region (20b, [0022] states, “…the second silicon carbide semiconductor layer 20 and the third silicon carbide semiconductor layer 30 are epitaxial layers formed by epitaxial growth.”) is an epitaxial growth layer formed on the first silicon carbide region (20a, [0021], FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hung into the structure of Tamaso in view of Schaeffer since Hung teaches a semiconductor device with silicon carbide integrated.
The ordinary artisan would have been motivated to modify Hung in combination with Tamaso in view of Schaeffer in the above manner for the motivation of forming the second silicon carbide region with an epitaxial growth process to help optimize the voltage levels in the semiconductor device. [0002] states, “A semiconductor power device generally requires for high breakdown voltage and has on-state resistance as small as possible, low reverse leakage current and relatively high switching speed to reduce conduction loss and switching loss during operation. As silicon carbide (SiC) is characterized in wide bandgap (Eg=3.26 eV), high critical breakdown field strength (2.2MV/cm), high thermal conductivity coefficient (4.9 W/cm-K) and the like, silicon carbide is considered to be an excellent material for a power switching device.”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Schaeffer et al. (US 20200013859 A1) and further in view of Sakai et al. (WO 2015025625 A1).
Re Claim 5 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 1, but does not teach the device region includes a first region and a second region surrounding the first region and provided along the dicing region, and
a maximum distance from the second face to the first face of the second region in the normal direction is greater than a maximum distance from the second face to the first face of the first region in the normal direction.
Sakai teaches the device region (10, page 7 par 1, “Silicon carbide semiconductor substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a.”) includes a first region (B) and a second region (A) surrounding the first region (B) and provided along the dicing region (DL, page 13 par 1, FIG. 8), and
a maximum distance from the second face (10b) to the first face (10a) of the second region (A, dA in annotated figure below) in the normal direction is greater than a maximum distance from the second face (10b) to the first face (10a) of the first region (B, dA in annotated figure below) in the normal direction.
Annotated FIG. 6C shown below with distances labeled.
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544
812
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Sakai into the structure of Tamaso in view of Schaeffer since Sakai teaches a semiconductor device with silicon carbide integrated.
The ordinary artisan would have been motivated to modify Sakai in combination with Tamaso in view of Schaeffer in the above manner for the motivation of integrating silicon carbide into a semiconductor device and optimally shaping the regions of the chip using varying thickness in the silicon carbide to help the device achieve a favorable breakdown voltage. Page 2 last par states, “Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/30/26