DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-4 and 6-13 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/27/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Hiyoshi (WO 2016152281 A1).
Tamaso teaches a semiconductor device (FIG. 11 and 21) comprising:
a device region (101, page 8 par 4); and
a dicing region (102, page 8 par 2) surrounding the device region (101, FIG. 4),
the device region (101) including a first electrode (94, page 11 par 5),
a second electrode (98, page 11 par 5), and
a silicon carbide layer (10, page 12 par 2) having a first face (10a, FIG. 12) on a side of the first electrode (10 is on bottom surface of 12 which is on bottom surface of 94) and a second face (10b) on a side of the second electrode (98), at least a portion of the silicon carbide layer (10) provided between the first electrode (94) and the second electrode (98).
Tomaso does not teach the dicing region including the silicon carbide layer having the first face and the second face, wherein a first maximum distance from the second face to the first face of the device region in a normal direction of the second face is greater than a second maximum distance from the second face to the first face of the dicing region in the normal direction,
the device region includes a first region and a second region surrounding the first region and provided along the dicing region,
a maximum distance from the second face to the first face of the second region in the normal direction is greater than a maximum distance from the second face to the first face of the first region in the normal direction, and
the maximum distance from the second face to the first face of the first region in the normal direction is greater than the second maximum distance.
Hiyoshi teaches the dicing region (DL, page 10 last par, FIG. 11) including the silicon carbide layer (use 12 which is part of 19, page 10 par 4 states, “silicon carbide epitaxial layer 19.”) having the first face (top of 12) and the second face (bottom of 12), wherein a first maximum distance (see drawing below) from the second face to the first face of the device region in a normal direction of the second face is greater than a second maximum distance (see drawing below) from the second face to the first face of the dicing region (DL) in the normal direction,
the device region (IR + OR combined, page 9 par 4) includes a first region (see drawing below) and a second region surrounding the first region and provided along the dicing region (DL),
a maximum distance (see drawing below) from the second face (bottom of 12) to the first face (top of 12) of the second region in the normal direction is greater than a maximum distance (see drawing below) from the second face (bottom of 12) to the first face (top of 12) of the first region in the normal direction, and
the maximum distance (see drawing below) from the second face (bottom of 12) to the first face (top of 12) of the first region in the normal direction is greater than the second maximum distance (see figure below).
Modified FIG. 11 shown below
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hiyoshi into the structure of Tamaso since Hiyoshi teaches a semiconductor device with a silicon carbide substrate.
The ordinary artisan would have been motivated to modify Hiyoshi in combination with Tamaso in the above manner for the motivation integrating silicon carbide into the semiconductor device to enable higher breakdown voltage, lower loss, and use in high-temperature environments. Page 2 par 3 states, “In recent years, silicon carbide has been increasingly adopted as a material constituting semiconductor devices in order to enable higher breakdown voltage, lower loss, and use in high-temperature environments.”
Re Claim 6 Tamaso in view of Hiyoshi teaches the semiconductor device according to claim 1, wherein the device region (Tomaso, 101) further includes an insulating layer (93, page 11 last par) provided on the first electrode (94, FIG. 20),
and at least a portion of an outermost surface of the dicing region (102) on a side of the first face (10a) is the silicon carbide layer (10, FIG. 11).
Re Claim 12 Tamaso in view of Hiyoshi teaches the semiconductor device according to claim 1, wherein the second face (Hiyoshi, bottom of 12) of the first region and the second face (bottom of 12) of the second region are in a same plane (see modified FIG. 11 under claim 1 for first region and second region).
Re Claim 13 Tamaso in view of Hiyoshi teaches the semiconductor device according to claim 1, wherein the first face (Hiyoshi, top of 12) of the second region includes a protruded portion (see modified FIG. 11 under claim 1, use left side of top surface of 12 along the first region).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Hiyoshi (WO 2016152281 A1) as applied to claim 1 above, and further in view of Schaeffer et al. (US 20200013859 A1).
Re Claim 2 Tomaso in view of Hiyoshi teaches the semiconductor device according to claim 1, wherein a difference between the first maximum distance and the second maximum distance is equal to or more than 0.5 μm.
Schaeffer teaches in [0153], “The splitting region 750 may have a thickness of at least 30 nm, typically at least 100 nm, and at most 1.5 μm, typically at most 500 nm.” FIG. 6C shows 750 is roughly 4x larger than d2-d1. If 750 is at least ~125nm, that would make d2-d1 at least ~500nm, .5 μm.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Schaeffer into the structure of Tamaso in view of Hiyoshi since Schaeffer teaches a semiconductor device with a silicon carbide substrate.
The ordinary artisan would have been motivated to modify Schaeffer in combination with Tamaso in view of Hiyoshi in the above manner for the motivation of finding optimal distance difference between the die region and device region thicknesses to optimize the device’s thickness to improve device characteristics. [0003] states, “Attempts have been made to reduce the final thickness of semiconductor material to improve device characteristics. For example, in power semiconductor devices with a vertical load current flow between a front side and a backside, a thinner semiconductor die may result in lower on-state resistance.” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal device region thickness vs dicing region thickness.
Re Claim 3 Tomaso in view of Hiyoshi and Schaeffer teaches the semiconductor device according to claim 1, wherein the silicon carbide layer (Schaeffer, 700) in the device region (650) includes a first silicon carbide region (139) [0168] of a first conductive type (n+) and a second silicon carbide region (131, not mentioned in text, shown on FIG. 9A) provided on the first silicon carbide region (700), the second silicon carbide region having a first-conductive-type impurity concentration (n-) different from a first-conductive-type impurity concentration of the first silicon carbide region (139), and
the first silicon carbide region (139) is in contact with the first face of the dicing region (use 706 [0188] as dicing region, FIG. FIG. 9A-D).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tamaso (WO 2015015937 A1, IDS) in view of Hiyoshi (WO 2016152281 A1) as applied to claim 1 above, and further in view of Hung et al. (US 20220223730 A1).
Re Claim 4 Tamaso in view of Schaeffer teaches the semiconductor device according to claim 3, but does not teach the second silicon carbide region is an epitaxial growth layer formed on the first silicon carbide region.
Hung teaches the second silicon carbide region (20b, [0022] states, “…the second silicon carbide semiconductor layer 20 and the third silicon carbide semiconductor layer 30 are epitaxial layers formed by epitaxial growth.”) is an epitaxial growth layer formed on the first silicon carbide region (20a, [0021], FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hung into the structure of Tamaso in view of Schaeffer since Hung teaches a semiconductor device with silicon carbide integrated.
The ordinary artisan would have been motivated to modify Hung in combination with Tamaso in view of Schaeffer in the above manner for the motivation of forming the second silicon carbide region with an epitaxial growth process to help optimize the voltage levels in the semiconductor device. [0002] states, “A semiconductor power device generally requires for high breakdown voltage and has on-state resistance as small as possible, low reverse leakage current and relatively high switching speed to reduce conduction loss and switching loss during operation. As silicon carbide (SiC) is characterized in wide bandgap (Eg=3.26 eV), high critical breakdown field strength (2.2MV/cm), high thermal conductivity coefficient (4.9 W/cm-K) and the like, silicon carbide is considered to be an excellent material for a power switching device.”
Response to Arguments
Applicant’s arguments with respect to claims 1-4 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/18/26
Prosecution Insights