DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
5. Applicant’s election without traverse of Group I, Claims 1-14 in the reply filed on 12/22/2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/22/2025.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-2, 5-6 and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cui, Zhixin et al. (Pub No. US 20220045091 A1) (hereinafter, Cui), and further in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani).
Re Claim 1, Cui teaches a semiconductor structure (Figs 24I/29B; Note: Figs 24I/29B refer to two separate embodiments of the claimed invention), comprising:
an alternating stack (Alternating stack; 132/146/246; Figs 24I/29B; ¶[0058]) of insulating layers (Insulating layers; 132; Figs 24I/29B; ¶[0085]) and electrically conductive layers (Conductive layers/sacrificial material layers; 146/246 and 142/242; Figs 24I/29B; ¶[0154]; Note: Sacrificial material layers of Fig 24I are later converted to electrically conductive layers);
a memory opening (Memory opening; 49; Fig 24A; ¶[0122]) vertically extending through the alternating stack;
a memory opening fill structure (Memory film/Semiconductor channel/Pillar channel portions/Pedestal channel portion/Semiconductor constriction rings; 50/60/311/11/216; Fig 29B; ¶[0162, 0196]) located in the memory opening and comprising a memory film (Memory film; 50; Fig 29B; ¶[0137]), a vertical semiconductor channel (Semiconductor channel; 60; Fig 29B; ¶[0171]), and a semiconductor cap structure (Pillar channel portions/Pedestal channel portion/Semiconductor constriction rings; 311/11/216; Fig 29B; ¶[0162, 0196]) comprising a semiconductor core structure (Pillar channel portions/Pedestal channel portion; 311/11; Fig 29B; ¶[0162]) contacting a bottom end (Bottom surface of 60; Fig 29B) of the vertical semiconductor channel and an annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 29B; ¶[0196]; Per the second embodiment of Fig 24I, the annular semiconductor structure is the vertical semiconductor channel 60 within insulating layers 170/180) laterally surrounding the semiconductor core structure and having a lesser vertical extent than the semiconductor core structure.
However, Cui does not teach a source layer contacting a bottom surface of the semiconductor core structure.
In the same field of endeavor, Sharangpani teaches a source layer (Source contact structure; 224; Fig 18C; ¶[0124]) contacting a bottom surface (Top surface of 124; Fig 18C) of the semiconductor core structure (Doped semiconductor portions; 124; Fig 17D; ¶[0129]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a source layer contacting a bottom surface of the semiconductor core structure, as disclosed by Sharangpani, with the semiconductor structure as taught by Cui. One would have been motivated to do this with a reasonable expectation of success because a medium between the source layer and the vertical semiconductor channels in the optimal configuration would be located in contact between them, such that the contact resistance between the source layer and vertical semiconductor channels may be reduced (Sharangpani, ¶[0146]).
Re Claim 2, Cui teaches the semiconductor structure of Claim 1, wherein the source layer (Lower source-level semiconductor layer; 112; Fig 29B; ¶[0075]) further contacts a bottom surface (Bottom surface of 212; ¶[0196]) of the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 29B; ¶[0196]).
Re Claim 5, Cui teaches the semiconductor structure of Claim 1, further comprising a semiconductor material layer (Upper source-level semiconductor layer; 116; Fig 29B; ¶[0075]) located between the alternating stack (Alternating stack; 132/146/246; Figs 24I/29B; ¶[0058]) and the source layer (Lower source-level semiconductor layer; 112; Fig 29B; ¶[0075]) and laterally surrounding the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 29B; ¶[0196]).
Re Claim 6, Cui teaches the semiconductor structure of Claim 5, wherein the memory film (Memory film; 50; Fig 29B; ¶[0137]) comprises:
a vertically-extending portion (Vertical portion of memory film 50; Fig 24I) that vertically extends through the alternating stack (Alternating stack; 132/146/246; Figs 24I/29B; ¶[0058]); and
a laterally-protruding portion (Laterally protruding portion of memory film 50 within insulating layers 170/180; Fig 24I) that is adjoined to a bottom end (Bottom end of insulating layer layer 232; Fig 24I) of the vertically-extending portion and laterally protruding outward from the bottom end of the vertically extending portion and laterally surrounding the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 29B; ¶[0196]; Per the second embodiment of Fig 24I, the annular semiconductor structure is the vertical semiconductor channel 60 within insulating layers 170/180; ¶[0214]).
Re Claim 9, Cui teaches the semiconductor structure of Claim 1, further comprising an insulating material layer (Upper sacrificial liner; 105; Fig 24I; ¶[0078]) located between the alternating stack (Alternating stack; 132/146/246; Figs 24I/29B; ¶[0058]) and the source layer (Lower source-level semiconductor layer; 112; Figs 24I/29B; ¶[0075]) and laterally surrounding the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Figs 24I/29B; ¶[0196]).
Re Claim 10, Cui teaches the semiconductor structure of Claim 1, wherein the semiconductor core structure (Pillar channel portions/Pedestal channel portion; 311/11; Fig 29B; ¶[0162]) protrudes downward below a horizontal plane including a bottom surface (Horizontal plane on level of bottom surface of 216; Fig 29B) of the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 29B; ¶[0196]).
Re Claim 11, Cui teaches the semiconductor structure of Claim 10, wherein the semiconductor core structure (Pillar channel portions/Pedestal channel portion; 311/11; Fig 29B; ¶[0162]) comprises a contoured bottom surface (Contoured lower surface of 11; Fig 24I) having a periphery (Outer edges; Fig 24I) that is located below a center point (Center point of 11; Fig 24I) of the contoured bottom surface.
Re Claim 12, Cui does not teach the semiconductor structure of Claim 1, wherein the semiconductor core structure comprises a horizontal bottom surface located within a same horizontal plane as a horizontally-extending portion of a bottom surface of the annular semiconductor structure.
In the same field of endeavor, Sharangpani teaches the semiconductor structure of Claim 1, wherein the semiconductor core structure (Backside semiconductor cap structure; 111; Fig 31D; ¶[0162]) comprises a horizontal bottom surface (Bottom surface of 111; Fig 31D) located within a same horizontal plane as a horizontally-extending portion of a bottom surface (Horizontal portion of bottom surface of 116 on the sides of 111; Fig 31D) of the annular semiconductor structure (Metal-semiconductor alloy structure; 116; Fig 31D; ¶[0172]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the semiconductor core structure comprising a horizontal bottom surface located within a same horizontal plane as a horizontally-extending portion of a bottom surface of the annular semiconductor structure, as taught by Sharangpani, with the semiconductor structure as taught by Cui. One would have been motivated to do this with a reasonable expectation of success because the semiconductor structure comprising a horizontal bottom surface within a same horizontal plane as the bottom surface as the annular semiconductor structure comprises of a shape which allows surface area contact between the semiconductor structure and annular semiconductor structure allowing reduced contact resistance from the vertical semiconductor channels to the backside conductive layer.
Re Claim 13, Cui teaches the semiconductor structure of Claim 12, wherein the bottom surface (Bottom surface of 212; Fig 24I) of the annular semiconductor structure (Semiconductor constriction rings/cap structure; 216/212; Fig 24I; ¶[0196]) comprises a tapered convex annular surface (Tapered surface which is convex inwards; 212; Fig 24I) adjoined to the horizontally-extending portion (Horizontal bottom surface of 212; Fig 24I) of the bottom surface of the annular semiconductor structure.
Re Claim 14, Cui does not teach the semiconductor structure of Claim 1, wherein the source layer comprises a metallic material.
In the same field of endeavor, Sharangpani teaches the semiconductor structure of Claim 1, wherein the source layer (Source contact structure; 224; Fig 18C; ¶[0124]) comprises a metallic material (Metallic barrier liner; 224B; Fig 18C; ¶[0124]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the source layer comprising a metallic material, as taught by Sharangpani, with the semiconductor structure as taught by Cui. One would have been motivated to do this with a reasonable expectation of success because an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for the source contact structure (Sharangpani, ¶[0096]).
8. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cui, Zhixin et al. (Pub No. US 20220045091 A1) (hereinafter, Cui) in view of Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani) as applied to claims 5 and 6 above, and further in view of Obu, Tomoyuki et al. (Pub No. US 20210265379 A1) (hereinafter, Obu).
Re Claim 7, Cui in view of Sharangpani does not teach the semiconductor structure of Claim 6, wherein the semiconductor material layer does not contact and is laterally spaced by the laterally-protruding portion of the memory film from the annular semiconductor structure.
In the same field of endeavor, Obu teaches the semiconductor structure of Claim 6, wherein the semiconductor material layer (Upper source-level semiconductor layer; 116; Fig 24; ¶[0059]) does not contact and is laterally spaced by the laterally-protruding portion (Convex portion of memory film 50 near dielectric spacers 53; Fig 24) of the memory film (Memory film; 50; Fig 24; ¶[0125]) from the annular semiconductor structure (Source region near dielectric spacers 53, i.e. may be considered an annular/cylindrical semiconductor structure from the plan view; Fig 24; ¶[0188]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the semiconductor material layer which does not contact and is laterally spaced by the laterally-protruding portion of the memory film from the annular semiconductor structure, as disclosed by Obu, with the semiconductor structure as taught by Cui in view of Sharangpani. One would have been motivated to do this with a reasonable expectation of success because the memory film in the upper convex portion of the source contact layer partially blocks the annular semiconductor structure such that current flow into the vertical channel layers above may be electrically isolated to provide a clear conductive path.
Re Claim 8, Cui in view of Sharangpani does not teach the semiconductor structure of Claim 5, wherein the source layer contacts a horizontal backside surface of the semiconductor material layer.
In the same field of endeavor, Obu teaches the semiconductor structure of Claim 5, wherein the source layer (Source contact layer; 114; Fig 24; ¶[0143]) contacts a horizontal backside surface (Lower surface of 116; Fig 24) of the semiconductor material layer (Upper source-level semiconductor layer; 116; Fig 24; ¶[0059]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the source layer contacts a horizontal backside surface of the semiconductor material layer, as taught by Obu, with the semiconductor structure as taught by Cui in view of Sharangpani. One would have been motivated to do this with a reasonable expectation of success because the source layer being connected to a surface of the semiconductor material layer allows for uniform voltage distribution across the vertical channel structures, minimizing read/writing errors in the three-dimensional memory device.
Allowable Subject Matter
9. Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest prior art Cui, Zhixin et al. (Pub No. US 20220045091 A1) (hereinafter, Cui) and Sharangpani, Rahul et al. (Pub No. US 20240349501 A1) (hereinafter, Sharangpani) either singularly or in combination fails to anticipate or render obvious
“The semiconductor core structure comprises a center seam that vertically extends from a center of a top surface thereof to a center of a bottom surface thereof; and
the semiconductor core structure comprises a contoured top surface having a periphery that is raised above a center point of the contoured top surface,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 3, the closest prior art Cui in view of Sharangpani discloses a semiconductor core structure with a contoured top surface, there is no center seam within the semiconductor core structure or any structure that may be rendered as a semiconductor core structure which may be comparable to that of the Applicant's disclosure. Therefore, the closest prior art in combination does not yield a predictable result given that the semiconductor core structure does not comprise of a center seam.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Okina, Teruo et al. (Pub No. US 20230284443 A1) discloses a semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.
[2] Kim, Kwang-Ho et al. (Pub No. US 11791327 B2) discloses a memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817