DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/15/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (U.S. PG Pub No US2019/0393206A1) (of record) in view of Kuneida (U.S. PG Pub No US2014/0360759A1).
Regarding claim 1, Wang teaches a semiconductor device (1) fig. 2 [0040] comprising:
a first power line (upper, horizontal VVdd) fig. 2 [0038];
a second power line (lower, horizontal VVdd) fig. 2 [0038];
a circuit region including a first region (R1) (see annotated fig. 2 below) in which a plurality of first power supply terminals (vertical Vdd in R1 with terminals 13) fig. 2 [0040] connected (through 12) [0040] to the first power line (upper, horizontal VVdd) are arranged at a first density in a planar view, and a second region (R2) (see annotated fig. 2 below) in which a plurality of second power supply terminals (vertical Vdd in R2 with terminals 13) fig. 2 [0040] connected to the first power line (upper, horizontal VVdd) are arranged at a second density that is lower than the first density in a planar view (more Vdd bumps 13 in R1 (4 bumps): total bumps in R1 (10 bumps) than Vdd bumps 13 in R3 (8 bumps) : total bumps in R2 (24 bump) (4:10> 8:24; 1/3<2/5 - as defined in annotated fig. 2 below);
a plurality of first bumps (10 total bumps 13) annotated fig. 2 below [0040] (13 shaped as bumps /protuberances relative to adjacent surfaces of lines Vdd/VVdd in plan view) in the first region (R1), and
a plurality of second bumps (24 total bumps 13) annotated fig. 2 below [0040] (13 shaped as bumps/ protuberances relative to adjacent surfaces of lines Vdd/VVdd in plan view) in the second region (R2), (as defined in R1, R2 in annotated fig. 2 below) wherein
the plurality of first bumps (13 in R1) include a plurality of first VDD bumps (4 VDD bumps 13) as the first power supply terminals [0040], and the plurality of second bumps (13 in R2) include a plurality of second VDD bumps (8 VDD bumps 13) as the second power supply terminals [0040];
a plurality of first power switch circuits (12’s in R1) see annotated fig. 2 below [0040] arranged in the first region (R1) and connecting the first power line (upper VVdd) to the second power line (lower VVdd); and
a plurality of second power switch circuits (12’s in R2) see annotated fig. 2 below [0040] arranged in the second region (R2) and connecting the first power line (upper VVdd) to the second power line (lower VVdd), wherein a (collective) second power supply capability to the second power line by a circuit (collective 12 in R2) including the first power line and the second power switch circuits (12 in R2) is higher than a first power supply capability to the second power line by a circuit (collective 12 in R1) including the first power line and the first power switch circuits (12 in R1) (four power switching circuits in R2 versus two in R1; collective power supply of circuitry of R2 greater than smaller R1 region, because more power circuitry in R2 - as defined in fig. 2 below),
the first density (4/10) is a ratio of a number of the plurality of first VDD bumps (4 VDD bumps 13 in R1) to a total number of the plurality of first bumps (10 bumps 13 in R1), and
the second density (8/24) is a ratio of a number of the plurality of second VDD bumps (8 VDD bumps 13 in R2) to a total number of the plurality of second bumps (24 bumps 13 in R2) (second density, 8/24 < 4/10, first density based on definitions of R1, R2 in annotated fig. 2 below).
[AltContent: connector][AltContent: textbox (R2)][AltContent: connector][AltContent: textbox (R1)][AltContent: rect][AltContent: rect]
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Annotated fig. 2 of Wang
However, Wang does not explicitly disclose the plurality of first bumps (13 in R1) and the plurality of second bumps (13 in R2) are provided on respective pads and on a surface side of the semiconductor device.
Kuneida teaches a semiconductor device (100) fig. 2 [0058-0059] wherein the plurality of first bumps (represented by left 38c’s with respective 41a’s with 42a’s with 43a’s) fig. 2 [0081-0082] (adjoined, interconnected conductive layers [0081-0082] considered as a single ‘bump’ structure) (see also annotated fig. 2 below, fig. 1C perspective for plurality [0075]) and the plurality of second bumps (represented by right 38c’s with respective 41a’s with 42a’s with 43a’s) fig. 2 [0081-0082] (see annotated fig. 2 below) are provided on (supported by) respective pads (respective 36a’s with 37c’s) fig. 2 [0060] and on (supported by) a surface side (internal surface side of B1 of 100) [0060] of the semiconductor device (100).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Second bumps)][AltContent: textbox (First bumps)][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: rect]
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Annotated fig. 2 of Kuneida
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductive bump-via structures [0081-0082] of Wang to comprise the conductive pads of Kuneida [0068] in order to enhance the overall interconnectivity of the semiconductor device [0068-0069] with the bump structures and adjacent circuitry [0068-0069] for improved power and signal transmission [0072-0075] throughout the device, as taught by Kuneida.
Regarding claim 2, Wang in view of Kuneida teaches the semiconductor device (1) [0040, 0048] according to claim 1. Wang also teaches wherein each of the plurality of the first power switch circuits (12’s in R1) see annotated fig. 2 above [0040] includes (is included with) a first transistor (comprising RSW1) fig. 7 [0049] [see fig. 8, 0048] connecting the first power line (upper VVdd / upper M 1002) fig. 7 [0049] to the second power line (lower VVdd / lower M 1002) fig. 7 [0049], each of the plurality of the second power switch circuits (12’s in R2) see annotated fig. 2 above [0040] includes (is included with) a second transistor (comprising RSW2) fig. 7 [0049] connecting the first power line (upper M1002) to the second power line (lower M1002), and a size of the second transistor (RSW2) fig. 7 [0049] is larger than a size of the first transistor (RSW1) fig. 7 [0049] (transistors positioned between VVdd lines [0048-0049]).
Regarding claim 3, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein each of the plurality of the first power switch circuits (12’s in R1) see annotated fig. 2 above [0040] and each of the plurality of the second power switch circuits (12’s in R2) see annotated fig. 2 above [0040] have a same circuit configuration (vertically-paired) with each other, and an arrangement density (number of 12-circuits per respective region) of the plurality of the second power switch circuits (# of 12’s in R2) is higher than an arrangement density of the plurality of the first power switch circuits (# of 12’s in R1) (as defined in annotated fig. 2 above).
Regarding claim 5, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein an arrangement density (total area of all VVdd’s + horizontal Vdd material in respective region) of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R2) fig. 2 [0038-0040] provided in the second region (R2) is higher than an arrangement density (total area of all VVdd’s + horizontal Vdd material in respective region) of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R1) provided in the first region (R1).
Regarding claim 6, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 5. Wang also teaches wherein an arrangement pitch (average Y-spacing of all horizontal Vdd’s in R2) fig. 2 [0038-0040] of the first power lines (comprising horizontal Vdd’s) provided in the second region (R2) is smaller than an arrangement pitch (average Y-spacing of all horizontal Vdd’s in R1) fig. 2 [0038-0040] of the first power lines (comprising horizontal Vdd’s) provided in the first region (R1).
Regarding claim 7, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 5. Wang also teaches wherein a number of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R2) fig. 2 [0038-0040] provided in the second region (R2) is larger than a number of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R1) provided in the first region (R1).
Regarding claim 8, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein a first parameter (P1 = (1/# of circuits 12 ) * (# of circuits 12 )) expressed by a product of an arrangement density (defined as 1/# of circuits 12 in R1) of the plurality of the first power supply terminals (vertical Vdd in R1 with terminals 13) fig. 2 [0040] in the first region (R1) and the first power supply capability (proportional to # of 12 circuits in R1), (P2 = P1 = 1, as defined) is equal to a second parameter (P2) expressed by a product of an arrangement density (defined as 1/# of circuits 12 in R2) of the plurality of the second power supply terminals (vertical Vdd in R2 with terminals 13) fig. 2 [0040] in the second region (R2) and the second power supply capability (proportional to # of 12 circuits in R2) (P2 = P1 = 1, as defined).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (U.S. PG Pub No US2019/0393206A1) (of record) modified by Kuneida (U.S. PG Pub No US2014/0360759A1), as applied in claim 1 above, in view of Dong (U.S. PG Pub No US2021/0376046A1) (of record).
Regarding claim 4, Wang in view of Kuneida teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. However, Wang does not explicitly disclose wherein a width of the first power line (upper, horizontal VVdd) fig. 2 [0038] provided in the second region (R2) is thicker than a width of the first power line (upper, horizontal VVdd) fig. 2 [0038] provided in the first region (R1) (shown with substantially-same widths).
Dong teaches a package semiconductor device [see fig. 5, 0155-0158] wherein a width (maximum) of the first power line (VDD3) fig. 5 [0122] provided in the second region (R2) is thicker than a width (minimum) of the first power line (VDD1) fig. 5 [0122] provided in the first region (R1) (due to variable widths of individual zig-zag shaped VDD’s in fig. 5 [0267, 0358-0359]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified individual of the power lines in Wang’s package to have a zig-zag structure with variable widths [0155-0158, 0267] in order to improve the versatility of circuitry layout [0358-0359] as well as reduce parasitic capacitance [0267, 038-0359], as taught by Dong.
Response to Arguments
Applicant’s arguments, see pages 1-2, filed 06/15/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kuneida (U.S. PG Pub No US2014/0360759A1) under 35 U.S.C. 103 for the inclusion of “pads”.
Further, with respect to Applicant’s arguments about a “surface side” of the semiconductor device, it is noted that the language of “a surface side” does little to distinguish over either Wang or Kuneida because, broadly, all surfaces (internal and external) of the semiconductor device can be considered as surface side(s) of the semiconductor device. The amendment does not specify what the recited “surface” corresponds to – an internal/inner surface, or an external/outermost surface of the semiconductor device?
Further, with respect to Applicant’s arguments about elements 13 of fig. 2 [0040] of Wang being “vias” rather than “bumps” – it is noted that claim 1 merely recites “bumps” without any limitations on the structure or composition of said bumps. Therefore, elements 13 of fig. 2 [0040] of Wang are considered to be reasonably interpreted as “bumps” in that they are shaped like bumps/protuberances relative to adjacent structures (i.e, likes Vdd/VVdd) in the plan view of fig. 2 of Wang.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are all considered relevant to the present disclosure because they all feature packages with power supply circuitry.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/26/2026
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