DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/15/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (U.S. PG Pub No US2019/0393206A1).
Regarding claim 1, Wang teaches a semiconductor device (1) fig. 2 [0040] comprising:
a first power line (upper, horizontal VVdd) fig. 2 [0038];
a second power line (lower, horizontal VVdd) fig. 2 [0038];
a circuit region including a first region (R1) (see annotated fig. 2 below) in which a plurality of first power supply terminals (vertical Vdd in R1 with terminals 13) fig. 2 [0040] connected (through 12) [0040] to the first power line (upper, horizontal VVdd) are arranged at a first density in a planar view, and a second region (R2) (see annotated fig. 2 below) in which a plurality of second power supply terminals (vertical Vdd in R2 with terminals 13) fig. 2 [0040] connected to the first power line (upper, horizontal VVdd) are arranged at a second density that is lower than the first density in a planar view (more vertical Vdd with 13 in R1 per unit area - as defined);
a plurality of first power switch circuits (12’s in R1) see annotated fig. 2 below [0040] arranged in the first region (R1) and connecting the first power line (upper VVdd) to the second power line (lower VVdd); and
a plurality of second power switch circuits (12’s in R2) see annotated fig. 2 below [0040] arranged in the second region (R2) and connecting the first power line (upper VVdd) to the second power line (lower VVdd), wherein a (collective) second power supply capability to the second power line by a circuit (collective 12 in R2) including the first power line and the second power switch circuits (12 in R2) is higher than a first power supply capability to the second power line by a circuit (collective 12 in R1) including the first power line and the first power switch circuits (12 in R1) (four power switching circuits in R2 versus two in R1; collective power supply of circuitry of R2 greater than smaller R1 region, because more power circuitry in R2 - as defined in fig. 2 below).
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Annotated fig. 2 of Wang
Regarding claim 2, Wang teaches the semiconductor device (1) [0040, 0048] according to claim 1. Wang also teaches wherein each of the plurality of the first power switch circuits (12’s in R1) see annotated fig. 2 above [0040] includes (is included with) a first transistor (comprising RSW1) fig. 7 [0049] [see fig. 8, 0048] connecting the first power line (upper VVdd / upper M 1002) fig. 7 [0049] to the second power line (lower VVdd / lower M 1002) fig. 7 [0049], each of the plurality of the second power switch circuits (12’s in R2) see annotated fig. 2 above [0040] includes (is included with) a second transistor (comprising RSW2) fig. 7 [0049] connecting the first power line (upper M1002) to the second power line (lower M1002), and a size of the second transistor (RSW2) fig. 7 [0049] is larger than a size of the first transistor (RSW1) fig. 7 [0049] (transistors positioned between VVdd lines [0048-0049]).
Regarding claim 3, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein each of the plurality of the first power switch circuits (12’s in R1) see annotated fig. 2 above [0040] and each of the plurality of the second power switch circuits (12’s in R2) see annotated fig. 2 above [0040] have a same circuit configuration (vertically-paired) with each other, and an arrangement density (number of 12-circuits per respective region) of the plurality of the second power switch circuits (# of 12’s in R2) is higher than an arrangement density of the plurality of the first power switch circuits (# of 12’s in R1) (as defined in annotated fig. 2 above).
Regarding claim 5, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein an arrangement density (total area of all VVdd’s + horizontal Vdd material in respective region) of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R2) fig. 2 [0038-0040] provided in the second region (R2) is higher than an arrangement density (total area of all VVdd’s + horizontal Vdd material in respective region) of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R1) provided in the first region (R1).
Regarding claim 6, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 5. Wang also teaches wherein an arrangement pitch (average Y-spacing of all horizontal Vdd’s in R2) fig. 2 [0038-0040] of the first power lines (comprising horizontal Vdd’s) provided in the second region (R2) is smaller than an arrangement pitch (average Y-spacing of all horizontal Vdd’s in R1) fig. 2 [0038-0040] of the first power lines (comprising horizontal Vdd’s) provided in the first region (R1).
Regarding claim 7, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 5. Wang also teaches wherein a number of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R2) fig. 2 [0038-0040] provided in the second region (R2) is larger than a number of the first power lines (comprising upper, horizontal VVdd and all horizontal Vdd’s in R1) provided in the first region (R1).
Regarding claim 8, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. Wang also teaches wherein a first parameter (P1 = (1/# of circuits 12 ) * (# of circuits 12 )) expressed by a product of an arrangement density (defined as 1/# of circuits 12 in R1) of the plurality of the first power supply terminals (vertical Vdd in R1 with terminals 13) fig. 2 [0040] in the first region (R1) and the first power supply capability (proportional to # of 12 circuits in R1), (P2 = P1 = 1, as defined) is equal to a second parameter (P2) expressed by a product of an arrangement density (defined as 1/# of circuits 12 in R2) of the plurality of the second power supply terminals (vertical Vdd in R2 with terminals 13) fig. 2 [0040] in the second region (R2) and the second power supply capability (proportional to # of 12 circuits in R2) (P2 = P1 = 1, as defined).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (U.S. PG Pub No US2019/0393206A1), as applied in claim 1 above, in view of Dong (U.S. PG Pub No US2021/0376046A1).
Regarding claim 4, Wang teaches the semiconductor device (1) fig. 2 [0040] according to claim 1. However, Wang does not explicitly disclose wherein a width of the first power line (upper, horizontal VVdd) fig. 2 [0038] provided in the second region (R2) is thicker than a width of the first power line (upper, horizontal VVdd) fig. 2 [0038] provided in the first region (R1) (shown with substantially-same widths).
Dong teaches a package semiconductor device [see fig. 5, 0155-0158] wherein a width (maximum) of the first power line (VDD3) fig. 5 [0122] provided in the second region (R2) is thicker than a width (minimum) of the first power line (VDD1) fig. 5 [0122] provided in the first region (R1) (due to variable widths of individual zig-zag shaped VDD’s in fig. 5 [0267, 0358-0359]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified individual of the power lines in Wang’s package to have a zig-zag structure with variable widths [0155-0158, 0267] in order to improve the versatility of circuitry layout [0358-0359] as well as reduce parasitic capacitance [0267, 038-0359], as taught by Dong.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they all feature packages with power supply circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 11/14/2025
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892