Prosecution Insights
Last updated: April 19, 2026
Application No. 18/450,115

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING INCLINED WORD LINE CONTACT STRIPS AND METHODS OF FORMING THE SAME

Non-Final OA §112
Filed
Aug 15, 2023
Examiner
PRIDEMORE, NATHAN ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Western Digital Technologies Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
94%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
45 granted / 61 resolved
+5.8% vs TC avg
Strong +20% interview lift
Without
With
+19.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
35 currently pending
Career history
96
Total Applications
across all art units

Statute-Specific Performance

§103
49.5%
+9.5% vs TC avg
§102
22.6%
-17.4% vs TC avg
§112
24.3%
-15.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 61 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (claims 1-15) in the reply filed on 12 January 2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 1, it recites “the topmost surface of the alternating stack” in the last line. This claim limitation lacks antecedence bases, leaving the claim unclear as to what the topmost surface of the alternating stack refers to. For at least this reason, claims 2-15 are also rejected under 35 USC 112(b) based on their dependency from claim 1. Regarding Claim 10, it recites “the topmost surface of the alternating stack” in the last line. This claim limitation lacks antecedence bases, leaving the claim unclear as to what the topmost surface of the alternating stack refers to. For at least this reason, claim 11 is also rejected under 35 USC 112(b) based on its dependency from claim 10. Regarding Claim 11, it recites “contacting topmost portions of the respective conductive strips” in line 7. It is unclear if this intends to refer to the same “a respective topmost portions” of the electrically conductive strips recited in claim 1. Regarding Claim 14, it recites “the at one support pillar structure” in the last line. This lacks antecedence and leaves the claim unclear as to what it refers to. It appears this should read “the at least one”. Appropriate correction is required. Allowable Subject Matter Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, and include all of the limitations of the base claim. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 1, the closest prior art of record (Tomohiro Kubo; US 2022/0102273 A1) teaches a memory device, comprising: an alternating stack (Fig. 3A; 132L/142L) including insulating layers (132L) and electrically conductive layers (142L become conductive layers 146) that are interlaced along a vertical direction (up/down), wherein the alternating stack comprises a tapered sidewall (Fig. 3A; tapered sidewall of 163) that laterally extends along a first horizontal direction and which is inclined along a second horizontal direction perpendicular to the first horizontal direction; memory openings (Fig. 9A; 49) vertically extending through each layer within the alternating stack; memory opening fill structures (Fig. 11A; 58) located in the memory openings and including a respective vertical stack of memory elements (Fig. 10D; 55/50) and a respective vertical semiconductor channel (60); a cavity (Fig. 9A; containing 165) in the alternating stack bounded laterally along a first side by the tapered sidewall (left side) and having a bottom surface comprising stepped surfaces of at least some of the electrically conductive layers (142 as shown on the right side of the cavity in Fig. 9A). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including an insulating liner located over the tapered sidewall in the cavity; and electrically conductive strips which are adjoined to a respective one of the stepped surfaces at the bottom surface of the cavity, which extend over the insulating liner and the tapered sidewall in the cavity, and which include a respective topmost portion that is located above the topmost surface of the alternating stack. For at least this reason, claims 2-15 would also be allowable based on their dependency from claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for relevant references, of which the instant claim 1 is distinct from. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NATHAN PRIDEMORE Examiner Art Unit 2898 /NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 15, 2023
Application Filed
Feb 09, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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POROUS III-NITRIDES AND METHODS OF USING AND MAKING THEREOF
2y 5m to grant Granted Mar 24, 2026
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SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581678
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE DEVICE
2y 5m to grant Granted Mar 17, 2026
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2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
94%
With Interview (+19.7%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 61 resolved cases by this examiner. Grant probability derived from career allow rate.

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