DETAILED ACTION
Response to Arguments
Applicant’s statements, invoking the prior art exception for commonly owned subject matter under AIA 35 U.S.C 102(b)(2)(C) have been fully considered and are persuasive. The rejections by Lin et al. (US 2023/0420493 A1) is withdrawn.
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new/different grounds of rejections by Tsai et al. (US 2021/0036097 A1) as set forth below in this Office Action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2021/0036097 A1; hereinafter “Tsai”).
Regarding claim 1, referring to Figs. 1-2, Tsai teaches an integrated circuit device, comprising: a substrate (103) (paragraph 13); and a trench capacitor structure (213) within the substrate (paragraph 16), comprising: a plurality of electrode layers (203A-203D) comprising a first material (for example, titanium nitride), wherein the first material has a first modulus of elasticity (a modulus of elasticity of titanium nitride) (paragraph 17); a plurality of insulator layers (205A-205C) interspersed with the plurality of electrode layers (paragraph 17); and a merged dielectric layer (a combination of 205D and 209) comprising a second material (for example, silicon oxide) that fills a merge region (a region where 205D and 209 are formed therein) between co-facing surfaces of a top-most electrode layer of the plurality of electrode layers (co-facing surfaces of 203D of 203A-203D) (paragraphs 17 and 21), wherein the second material is a single material (silicon oxide is a single material) that has a second modulus of elasticity that is lesser relative to the first modulus of elasticity (a modulus of elasticity of silicon oxide is less than the modulus of elasticity of titanium nitride as a material property) (paragraphs 17 and 21), and wherein the merged dielectric layer is in direct contact with the co-facing surfaces of the top-most electrode layer (the combination of 205D and 209 is in direct contact with the co-facing surfaces of 203D) (Fig. 2).
Regarding claim 2, Tsai teaches wherein a depth of each trench of the trench capacitor structure is greater relative to a width of each trench of the trench capacitor structure (for example, D1 is greater than W1) (Fig. 1 and paragraph 14).
Regarding claim 3, Tsai teaches wherein the first material comprises a titanium nitride material, and wherein the second material comprises: an oxide material (paragraphs 17 and 21).
Regarding claim 4, Tsai teaches wherein the oxide material comprises: an aluminum oxide material, a zirconium oxide material, or a silicon dioxide material (paragraph 21).
Regarding claim 5, Tsai teaches wherein the substrate comprises: a third material having a third modulus of elasticity (for example, 103 formed of silicon having a modulus of elasticity) (paragraph 13), wherein the third modulus of elasticity is lesser relative to the first modulus of elasticity (the modulus of elasticity of silicon is less than the modulus of elasticity of titanium nitride as a material property), and wherein the third modulus of elasticity is greater relative to the second modulus of elasticity (the modulus of elasticity of silicon is greater than the modulus of elasticity of silicon oxide as a material property).
Regarding claim 6, Tsai teaches wherein a ratio of the third modulus of elasticity to the second modulus of elasticity is greater than approximately 5:2 (considering 180GPa as the modulus of elasticity of silicon in an average range of 130-185 GPa and 60GPa as the modulus of elasticity of silicon oxide in an average range of 60-75 GPa, 180:60 is 3:1, which is greater than 5:2).
Regarding claim 7, referring to Figs. 1-2, Tsai teaches an integrated circuit device, comprising: a substrate (103) (paragraph 13); a trench capacitor structure (213) within the substrate (paragraph 16), comprising: a plurality of electrode layers (203A-203D) comprising a first material (for example, titanium nitride), wherein the first material has a first coefficient of thermal expansion (a coefficient of thermal expansion (CTE) of titanium nitride) (paragraph 17); a plurality of insulator layers (205A-205C) interspersed with the plurality of electrode layers (paragraph 17); and a merged dielectric layer (a combination of 205D and 209) comprising a second material (for example, silicon oxide) that fills a merge region (a region where 205D and 209 are formed therein) between co-facing surfaces of a top-most electrode layer of the plurality of electrode layers (co-facing surfaces of 203D of 203A-203D) (paragraphs 17 and 21), wherein the second material is a single material (silicon oxide is a single material) that has a second coefficient of thermal expansion that is lesser relative to the first coefficient of thermal expansion (a CTE of 209 formed of silicon oxide is less than the CTE of titanium nitride as a material property) (paragraphs 17 and 21), and wherein the merged dielectric layer is in contact with the co-facing surfaces of the top-most electrode layer (the combination of 205D and 209 is in contact with the co-facing surfaces of 203D) (Fig. 2).
Regarding claim 8, Tsai teaches wherein the first material comprises: a titanium nitride material (paragraph 17).
Regarding claim 10, Tsai teaches wherein the merged dielectric layer excludes co-facing surfaces in contact with each other and that form an interface (Fig. 2).
Regarding claim 11, Tsai teaches wherein the merged dielectric layer is on a top-most insulator layer (205C) of the plurality of insulator layers (Fig. 2).
Regarding claim 12, Tsai teaches wherein the merged dielectric layer includes a portion (a top portion of the combination of 205D and 209) outside the merge region (Fig. 2) and further comprising: an interconnect structure (307A-307E) passing through the portion and to the top-most electrode layer of the plurality of electrode layers (Fig. 3 and paragraph 23).
Regarding claim 13, Tsai teaches wherein the substrate comprises: a third material having a third coefficient of thermal expansion (for example, 103 formed of germanium having a CTE), wherein the third coefficient of thermal expansion is lesser relative to the first coefficient of thermal expansion (the CTE of germanium less than the CTE of titanium nitride as a material property), and wherein the third coefficient of thermal expansion is greater relative to the second coefficient of thermal expansion (the CTE of germanium is greater than the CTE of silicon oxide as a material property).
Regarding claim 14, Tsai teaches wherein a ratio of the third coefficient of thermal expansion to the second coefficient of thermal expansion is greater than approximately 7:1 (considering 6 as the CTE of germanium in an average range of 5.8-6 ppm/oC and 0.5 as the CTE of silicon oxide in an average range of 0.5-0.6 ppm/oC, 6:0.5 is greater than 7:1).
Regarding claim 15, referring to Figs. 1-2, Tsai teaches a method, comprising: forming an insulator layer (205A-205C) of a trench capacitor structure (213) on a device region (a region where 213 is formed) including a first material having a first coefficient of thermal expansion (for example, aluminum oxide having a coefficient of thermal expansion (CTE)) (paragraphs 13-17); forming an electrode layer (203A-203D) of the trench capacitor structure on the insulator layer from a second material having a second coefficient of thermal expansion that is greater relative to the first coefficient of thermal expansion (for example, copper has a CTE greater than aluminum oxide as a material property) (paragraph 17); and forming a merged dielectric layer (a combination of 205D and 209) that fills a gap (a gap where 205D and 209 are formed therein) between co-facing surfaces of the electrode layer (co-facing surfaces of 203D) from a third material having a third coefficient of thermal expansion that is lesser relative to the first coefficient of thermal expansion (silicon oxide has a CTE less than the CTE of aluminum oxide as a material property) (paragraphs 17 and 21), wherein the third material is a single material (silicon oxide is a single material) (paragraph 21), and wherein the merged dielectric layer is in contact with the co-facing surfaces of the electrode layer (the combination of 205D and 209 is in contact with the co-facing surfaces of 203D) (Fig. 2).
Regarding claim 16, Tsai teaches wherein forming the merged dielectric layer in the gap from the second material includes: using an atomic layer deposition process (paragraph 22).
Regarding claim 17, Tsai teaches wherein forming the merged dielectric layer in the gap from the second material includes: using a high aspect ratio process, wherein the high aspect ratio process includes a chemical vapor deposition process or a physical vapor deposition process (paragraph 22, CVD).
Regarding claim 19, Tsai teaches wherein forming the merged dielectric layer in the gap from the second material includes forming a lateral portion of the merged dielectric layer (a lateral portion of 209) over the insulator layer (Fig. 2).
Regarding claim 20, Tsai teaches further comprising: forming a cavity (a cavity where 307A-307E are formed therein) through the lateral portion of the second material and through insulator layer to expose an electrode layer; and forming an interconnect structure (307A-307E) in the cavity that connects with the electrode layer (Fig. 3 and paragraph 23).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Regarding claim 9, Tsai does not explicitly teach that the second material for the merged dielectric layer comprises a polyimide material. Nevertheless, it would have been obvious to one of ordinary skill in the art to utilize the polyimide material as the readily available organic dielectric material known in the art in place of inorganic dielectric materials such as silicon oxide or silicon nitride in order to obtain the predictable dielectric characteristics.
Regarding claim 18, Tsai does not explicitly teach that forming the merged dielectric layer in the gap from the second material includes: a deposition operation having a thermal cycle that includes a cooling duration. Nevertheless, it would have been obvious to one of ordinary skill in the art to recognize, after a review of Tsai’s teaching of the deposition method such as CVD and/or ALD for the merged dielectric layer (paragraphs 17 and 21-22), that the CVD and/or the ALD processing includes the thermal cycle including heating and cooling durations for its depositing operation.
Furthermore, since Tsai teaches each and every method steps for the trench capacitor structure structurally and compositionally identical to that of the claim, the claimed property (i.e., “wherein the cooling duration introduces a shrinkage strain within the trench capacitor structure based on a combination of the first coefficient of thermal expansion, the second coefficient of thermal expansion, and the third coefficient of thermal expansion” would be also identical: Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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