DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2020/0027917, in view of Miyairi et al. (“Miyairi”), WO2021166684 (the counterpart US publication US 2023/0072941 provides a translation and is used infra for citations).
Regarding Claim 11, Kim discloses a semiconductor structure (100; Figs. 5-6, 11B, 22A-B; ¶ 0041, 0109), comprising:
light-emitting structure layers (LED1, LED2, LED3; Fig. 6; ¶ 0044 “Each of the first to third semiconductor light emitting units LED1 to LED3 may include a light emitting structure 121 including a first conductivity type semiconductor layer 121a, a second conductivity type semiconductor layer 121c, and an active layer 121b located therebetween.”) and holes (111, 112, 113; Figs. 22A-B; ¶ 0125 “111 to 113 may include through holes penetrating to first surface (PL1 of FIGS. 5 and 6) from the second surface (PL2_SUB of FIGS. 5 and 6) of the substrate 110a” note that the outside wall of the holes are 111, 112, 113 and those holes are filled with first to third wavelength converting units 171, 172, 173) that are stacked (Figs. 22A-B), wherein the holes are located on a light-emitting side of the light-emitting structure layers (Figs. 6, 22A-B; ¶ 0042, 0125 “first to third light emitting windows 111 to 113 may be formed by etching some regions of the substrate 110a corresponding to the first to third semiconductor light emitting units LED1 to LED3”); and
second inhibition layers (119; Fig. 11B; ¶ 0096 “molding unit 140 covering the light emitting structure 121 may be buried in the recess portion 119” ¶ 0053 “molding unit 140 may be formed of a material including an epoxy resin or a silicone resin” therefore molding 140 in recesses 119 are inhibition layers), wherein the second inhibition layers are respectively located between two adjacent holes of the holes (Fig. 11B in this instance 119 is between holes that are shown as filled with 172 and 173).
Kim does not disclose wherein materials of the second inhibition layers comprise SiO2, SiN, or both, and the second inhibition layers do not cover the light-emitting structure layers.
Miyairi discloses wherein materials of the second inhibition layers (150; Fig. 2A; ¶ 0061) comprise SiO2 (¶ 0061 “Silicon oxide (SiO.sub.2)…used as the light-reflective material of the wall 150.”), SiN, or both, and the second inhibition layers do not cover the light-emitting structure layers (Fig. 2A; ¶ 0060 “light-emitting element 120…are surrounded by the wall 150. The wall 150 has a tubular shape.”, ¶ 0064 “the inner surface 150b surrounds the light-emitting element 120”, therefore the second inhibition layers 150 do not cover the top or bottom of the light emitting structure layers 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein materials of the second inhibition layers comprise SiO2, SiN, or both, and the second inhibition layers do not cover the light-emitting structure layers, as taught by Miyairi, because “light L2 propagates from the region of the inner surface 150b of the wall 150 adjacent to the wavelength conversion layer 130” (Miyairi ¶ 0071) thereby improving the performance of the semiconductor structure (Miyairi ¶ 0071-0074).
Regarding Claim 12, Kim discloses further comprising:
a color converting layer (171, 172, 173; Fig. 22B; ¶ 0126) located in each of the holes (Fig. 22B; ¶ 0126).
Regarding Claim 13, Kim discloses further comprising:
an insulation layer (140; Fig. 6; ¶ 0053 “140 may be formed of a material including an epoxy resin or a silicone resin”) located between two adjacent light-emitting structure layers of the light-emitting structure layers (Figs. 6, 11A; ¶ 0051 note that Fig. 11A shows separate locations for 119 and 140).
Regarding Claim 14, Kim discloses wherein a material of the insulation layer is a transparent material or a non-transparent material (¶ 0053 “140 may be formed of a material including an epoxy resin or a silicone resin”).
Regarding Claim 15, Kim discloses wherein when the material of the insulation layer is transparent material (¶ 0053 in this instance the resin material 140 includes “light reflective particles for reflecting light” so 140 implicitly is at least partially transparent material).
Kim does not specifically disclose a ratio of a projected area of the second inhibition layers on a horizontal plane to a projected area of the light-emitting structure layers on the horizontal plane is greater than or equal to 1, and the horizontal plane is parallel to an arranging direction of the second inhibition layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have a ratio of a projected area of the second inhibition layers on a horizontal plane to a projected area of the light-emitting structure layers on the horizontal plane is greater than or equal to 1, and the horizontal plane is parallel to an arranging direction of the second inhibition layers because adjusting the ratio of the second inhibit layer and the LED stack would allow for reduced cross-talk (interference) between adjacent pixels. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, adjusting the ratio to be 1 or greater would be a matter of routine optimization.
Regarding Claim 16, Kim does not specifically disclose wherein at least two of the light-emitting structure layers have different cross-sectional areas. However, Kim shows in Fig. 8B and discloses in ¶ 0074 that “In this arrangement…the size of the first to third subpixels SP1a to SP3a may be greater” (note that subpixels SP1a to SP3a correlate to LED1-LED3 in Fig. 6). Similarly, Kim shows in Fig. 8A and discloses in ¶ 0073 that “first and second subpixels SP1a and SP2a may be arranged to have a larger size than in other cases”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have at least two of the light-emitting structure layers have different cross-sectional areas in the same configuration of the semiconductor structure to provide design flexibility in order to optimize the lighting in different areas of semiconductor structure as needed.
Regarding Claim 17, Kim discloses wherein the light-emitting structure layers emit blue light (Fig. 6; ¶ 0065 “the first to third semiconductor light emitting units (LED1 to LED3) emit blue light”), and the color converting layers comprise at least one of: yellow quantum dots, yellow phosphors, red quantum dots, red phosphors, green quantum dots or green phosphors (¶ 0063 “wavelength converting units 172 and 173 may include green and red phosphors P2 and P3, respectively”).
Regarding Claim 18, Kim discloses further comprising:
a reflection layer (140; Fig. 6; ¶ 0053 “140 may include light reflective particles for reflecting light”) located on a side of each of the light-emitting structure layers far from the holes (Fig. 6; ¶ 0051).
Regarding Claim 19, Kim discloses wherein one of the light-emitting structure layers comprises a first semiconductor layer (121a; Fig. 6; ¶ 0044), an active layer (121b; Fig. 6; ¶ 0044) and a second semiconductor layer (121c; Fig. 6; ¶ 0044) that are stacked (Fig. 6), wherein the active layer is located on a side of the first semiconductor layer far from a substrate (Fig. 6; ¶ 0045 “the first conductivity type semiconductor layer 121a is formed and then the active layer 121b and the second conductivity type semiconductor layer 121c are formed” therefore 121b is on a side of 121a that is far from substrate 110), and a conductive type of the second semiconductor layer is opposite to a conductive type of the first semiconductor layer (¶ 0044 “a first conductivity type semiconductor layer 121a, a second conductivity type semiconductor layer 121c”); and
the semiconductor structure further comprises:
a first electrode (128; Fig. 5; ¶ 0048) and a second electrode (129; Fig. 5; ¶ 0048), wherein the first electrode penetrates the second semiconductor layer and the active layer (Fig. 5), and is electrically connected to the first semiconductor layer (¶ 0048 “first electrode 128 and a second electrode 129 may be electrically connected to the first conductivity type semiconductor layer 121a and the second conductivity type semiconductor layer 121c, respectively”), and the second electrode is electrically connected to the second semiconductor layer (¶ 0048 “first electrode 128 and a second electrode 129 may be electrically connected to the first conductivity type semiconductor layer 121a and the second conductivity type semiconductor layer 121c, respectively”).
Regarding Claim 20, Kim discloses further comprising:
a second light-emitting structure layer (180; Fig. 5; ¶ 0064 providing desired lights) in each of the holes, wherein the second light-emitting structure layer is on a light-emitting side of the corresponding light-emitting structure layer (Fig. 5).
Allowable Subject Matter
Claims 1-10 are allowed.
Regarding Claim 1, the prior art does not teach or render obvious providing second inhibition layers, wherein the second inhibition layers are respectively located between two adjacent columnar structures of the columnar structures, and upper surfaces of the columnar structures are exposed and in the combination as claimed.
The closest prior art appears to be Dimitropoulos et al. (“Dimitropoulos”), US 2021/0020806. Dimitropoulos discloses a manufacturing method (600; Fig.6A; ¶ 0070) of a semiconductor structure (500; Fig. 5K; ¶ 0070), comprising: providing a patterned substrate (505; Figs. 5A; ¶ 0045, 0072), wherein the patterned substrate comprises columnar structures (Fig 5A; ¶ 0046 “the first flat portion may be vertically offset from the second flat portion”); providing a light-emitting structure layer (epi layer that includes layers 510, 515, 520; Fig. 5B; ¶ 0073) on the upper surface of each of the columnar structures (Fig. 5B; ¶ 0073); and removing the patterned substrate (Fig. 5I; ¶ 0080), to obtain holes at regions corresponding to the columnar structures (Fig. 5I; ¶ 0080 “pockets”), wherein the holes are respectively located between two adjacent second inhibition layers of the second inhibition layers (Fig. 5I; ¶ 0080), and the holes correspond to the light-emitting structure layers respectively (Fig. 5I; ¶ 0080 “Once removed, n-layer 510 may be exposed.”).
Dimitropoulos does not disclose providing second inhibition layers, wherein the second inhibition layers are respectively located between two adjacent columnar structures of the columnar structures, and upper surfaces of the columnar structures are exposed. For example, providing inhibition layers (530; Fig. 5D; ¶ 0075 “530 may entirely surround each LED”) before providing a light-emitting structure layer (epi layer that includes layers 510, 515, 520; Fig. 5B; ¶ 0073) on the upper surface of each of the columnar structures would cause the light-emitting structure layer to not be properly formed.
Claims 2-10 are allowable for depending on Claim 1.
Response to Arguments
The Applicant states (page 8) that “the material of the second inhibition layer in claim 1 includes SiO2, SiN, or a combination of SiO2 and SiN, which are organic. Therefore, the molding unit 140 of Kim is completely different from the second inhibition layer of claim 1.”
It is assumed that the Applicant meant “claim 11” instead of “claim 1” because Claim 1 does not include “SiO2, SiN, or a combination of SiO2 and SiN”.
The amendments to Claim 11 has necessitated an updated rejection of Claim 11. Claim 11 is now rejected over the combination of Kim and Miyairi.
As explained supra, Miyairi discloses wherein materials of the second inhibition layers (150; Fig. 2A; ¶ 0061) comprise SiO2 (¶ 0061 “Silicon oxide (SiO.sub.2)…used as the light-reflective material of the wall 150.”).
It is noted that the second inhibition layers 122 of Fig. 8 of the pending application are between color converting layers 16 inside holes 18. Similarly, the second inhibition layers 119 of Kim Fig. 11B are between wavelength converting units 172, 173 inside holes 112, 113 (Kim ¶ 0025-0026).
The Applicant states (page 10) that “the function of the molding unit 140 is different from that of the second inhibition layer.”
Even if the function of molding 140 located in second inhibition layers 119 has a different purpose, the second inhibition layers 119 will also be able to provide other functions listed on page 10 as “described in paragraph 66 of the specification”, such as “improving the quality of the light-emitting structure layer” and layers 119 “can protect the light-emitting structure layer”.
The Applicant states (page 10) that “Kim’s molding unit 140…is not inorganic SiO2/SiN barriers positioned between holes and not covering the LEDs as recited by claim 11.”
As explained supra, Miyairi discloses wherein materials of the second inhibition layers (150; Fig. 2A; ¶ 0061) comprise SiO2 (¶ 0061 “Silicon oxide (SiO.sub.2)…used as the light-reflective material of the wall 150.”), SiN, or both, and the second inhibition layers do not cover the light-emitting structure layers (Fig. 2A; ¶ 0060 “light-emitting element 120…are surrounded by the wall 150. The wall 150 has a tubular shape.”, ¶ 0064 “the inner surface 150b surrounds the light-emitting element 120”, therefore the second inhibition layers 150 do not cover the top or bottom of the light emitting structure layers 120).
Regarding pages 8 and 10-11, there are multiple references to “molding unit 140” of Kim. Molding unit 140 of Kim is located in the cell array CA (Fig. 6; ¶ 0051). Conversely, the molding unit material “buried in the recess portion 119” (Fig. 11B; ¶ 0096) that are the second inhibition layers are located in region OP3 (Fig. 11B).
The Applicant states (page 11) that “According to MPEP § 2143, obviousness requires an articulated reasoning with some rational underpinning.”
As explained supra, Kim does not specifically disclose wherein at least two of the light-emitting structure layers have different cross-sectional areas. However, Kim shows in Fig. 8B and discloses in ¶ 0074 that “In this arrangement…the size of the first to third subpixels SP1a to SP3a may be greater” (note that subpixels SP1a to SP3a correlate to LED1-LED3 in Fig. 6). Similarly, Kim shows in Fig. 8A and discloses in ¶ 0073 that “first and second subpixels SP1a and SP2a may be arranged to have a larger size than in other cases”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have at least two of the light-emitting structure layers have different cross-sectional areas in the same configuration of the semiconductor structure to provide design flexibility in order to optimize the lighting in different areas of semiconductor structure as needed.
Independent Claim 11 is rejected for at least the reasons stated supra. Dependent Claims 12-20 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818