DETAILED ACTION
Response to Amendments
The Amendment filed September 03/23/2026 has been entered. Claims 2, 3, 8, 11, 16, 17, and 19 are amended. Examiner notes the addition of Claim 21. Claims 1-21 are pending in the application. Examiner withdraws the specification objections to the captions for Figures 5, 6, 8 and 9, and for the reference numeral for the plurality of transistors. Examiner further acknowledges the amendment to claim 16 overcomes the 112(f) limitation and that the claim objections to Claim 8 and Claim 11 have been overcome. Applicant’s amendment to recite “a second pattern density” and “a third pattern density” in claims 2 and 3, respectively, overcome the previously made rejection under 112(b) regarding insufficient antecedent basis.
Response to Arguments
Applicant's arguments filed 03/23/2026 have been fully considered but they are not found to be persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In response to applicant's first argument that that even if Chen was combinable with the Uehira and Onuki (which examiner maintains is combinable under MPEP 2143.01), that Chen does not disclose the pattern density to be in the spatial placement as required in Claims 1 and 17, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant’s argument is not found persuasive, as the teaching of Chen were used for a dummy pattern density and numerical limitations, not towards reproducing the structure as claimed. A reference is not required to disclose an identical arrangement as the claimed invention for it to be applicable based on its teachings. A person of ordinary skill in the art before the effective filing date would be able to use the numerical dummy pattern density taught by Chen and apply it to the teachings of Uehira, as modified by Onuki, which do accurately relay the correct spatial locations of the recited elements, for the known benefit of creating a flatter, more bondable surface.
In response to applicant’s second argument that Chen teaches away from the claimed invention, as Chen suggests a dummy pattern or 40% or less, for the purpose of improving bonding quality, applicant’s assertion is not found persuasive. Chen does not discredit or teach away the pattern density for an overlapping portion with the applicants claimed range (namely, 35% - 40%). As there is an overlap in the applicant’s claimed range and the prior art, a prima facie case of obviousness exists (see MPEP 2131.03 and 2144.05) and therefore Chen does not teach away, but mainly discloses an optimization within a working, broader range. A person of ordinary skill in the art would be motivated to be provide a pattern density between 35% - 40%, as disclosed by Chen, and meeting the invention as claimed (35% or more) in Claims 1 and 17.
In response to applicant’s third argument that the claimed pattern density is not considered routine design consideration as the cited references do not address the problem of measurement errors, applicant’s argument is found not persuasive. Obviousness does not require a cited reference/prior art to be used with the identical stated purpose or motivation supplied by the Applicant. The rationale for obviousness is related to whether a person of ordinary skill in the art would be motivated to or reasonably suggested by the prior art for any recognized benefit, or a predictable result. In this case, Chen discloses the use of wiring pattern densities within a known range, making it a result-effective variable, for the purpose of achieving a flatter, bondable surface and/or achieving an improved bonding quality, which is the predictable result. Selecting a wiring pattern density of 35%-40%, which overlaps the claimed range (35% or more) of Claims 1 and 17, is therefore a choice a person of ordinary skill in the art could make to optimize a known parameter (routine design choice), and arrive at the invention as claimed. The fact that the applicant may utilize the claimed pattern density for an alternate purpose, such as preventing measurement errors during the manufacturing process, does not render the teachings of Chen unapplicable for routine design optimization as it already teaches and motivates optimization of the same parameter (wiring pattern density) within the claimed range (35% or more).
In addition to the arguments above, which apply to independent Claim 17, applicant further argues for claim 17 that the in-situ measurement method of Coult does not address the specific problem specified by the applicant, namely that Coult does not disclose the risk of erroneous detection caused by reflected light from deeper layers when the wiring density is low. Applicant’s argument is found not persuasive for the reason of: applicant’s argument is directed towards an unclaimed advantage or intended use. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Coult teaches the method steps of thinning the semiconductor layer from a side of a light receiving surface on an opposite side to a main surface where a plurality of wiring layers are arranged, wherein a plurality of wiring patterns are arranged in a wiring layer closest to the main surface among the plurality of wiring layers, in the thinning, a film thickness of the semiconductor layer is measured by using reflected light of light irradiated onto the light receiving surface, which are substantially identical method steps as those claimed in Claim 17, and therefore the prior art is capable of achieving the intended purpose. As such, the examiner maintains that the teachings of Coult can be further applied in combination with the teachings of Chen.
Therefore, for at least the above reasons, Examiner maintains that Uehira, Onuki, and Chen can be reasonably combined to meet the invention as claimed of independent Claim 1 and the addition of Coult can be further used with the teachings of Uehira, Onuki, and Chen to meet the invention as claimed of independent Claim 17. The dependent claims using the additional previously cited references are therefore also properly rejected.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “second pattern density” as set forth in claim 2, “third pattern density” as set for in claim 3, “fourth pattern density” as set forth in claim 19, and “first semiconductor component” and “second semiconductor component” as set forth in claim 21, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 2, 16 and 21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1) and further in view of Chen (US 9,412,725 B2).
Re: Independent Claim 1, Uehira discloses a photoelectric conversion apparatus (Uehira, photoelectric conversion device; ¶ [0064], Fig. 1A , element 010) comprising a semiconductor layer (Uehira, semiconductor layer; ¶ [0064], Fig. 2, elements 520 and 200), a pixel region in which a plurality of pixels each comprising a photoelectric conversion element are arranged (Uehira, pixel portion in which pixels having a light-receiving portion are arranged so as to be lined up in a plurality of rows and a plurality of columns; ¶ [0064], Fig.1A, element 011), comprising a photoelectric conversion element are arranged (Uehira, avalanche photodiode; ¶ [0008]), wherein
a plurality of wiring layers (Uehira, plurality of wiring layers; ¶ [0067], Fig. 2, element 530 and element 300), are arranged on a side of a main surface (Uehira, front surface; Fig. 2, element 201) on the opposite side to a light receiving surface of the semiconductor layer (Uehira, rear surface; Fig. 2, element 202)
Uehira further discloses a peripheral circuit portion (Uehira, peripheral circuit portion; ¶ [0078], not illustrated in figures) in the semiconductor layer.
Uehira is silent regarding:
and a pattern density of the wiring patterns arranged in a peripheral region between the pixel region and an outer edge of the semiconductor layer among the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region
Onuki discloses:
a pattern density (Onuki, wiring density of a wiring pattern; ¶ [0005], Fig. 5A) of the wiring patterns (Onuki, wiring layer (Fig. 4, element 122) includes one or more wiring patterns; ¶ [0043], Fig. 5A, elements 242A, 242B) arranged in a peripheral region (Onuki, a peripheral region; Fig. 5A, element 102) between the pixel region (Onuki, the pixel region; element 100, Fig. 5A) and an outer edge of the semiconductor layer (Onuki, semiconductor element layer; Fig. 4, element 11).
Onuki further discloses that the first wiring pattern located in a region aligned with the pixel region has a higher wiring density than the wiring pattern aligned with the peripheral region (Onuki, ¶ [0005]).
Uehira discloses a peripheral circuit region and wiring layers in the photoelectric conversion device. Onuki discloses wiring layers having wiring patterns with pattern densities to reduce the influence of coupling due to potential fluctuation in the electric-circuit chip, (Onuki, ¶ [0057]). Although Uehira discloses that the peripheral circuit portion can be arranged on the semiconductor layer without necessarily including a wiring layer, a person of ordinary skill in the art (POSITA) before the effective filing date of the claimed invention would have recognized the peripheral circuit portion of Uehira as a candidate for the peripheral region used in Onuki. It would be obvious to include the modifications of the wiring density of the wiring patterns in Onuki to allow the wiring pattern to have a low impedance and influence of coupling due to potential fluctuations of the electric-circuit chip in the arrangement of the wiring patterns, reducing the degradation of characteristics caused by smear and shading (Onuki, ¶ [0057]).
Uehira, as modified by Onuki, still fails to disclose:
the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region.
Chen discloses the numerical pattern density or 40% or less (Chen, Column 4, lines 50-51), though only for a dummy pattern. The density taught by dummy patterns is directly applicable to wiring patterns, as both occupy patterned areas within the wiring layer. It would have been obvious to a POSITA before the effective filing date of the claimed invention to select a wiring pattern density (which can include dummy and functional patterns) within the 35% – 40% range in an arbitrary 100 μm2 region of the peripheral region, and apply it to Uehira, as modified by Onuki, since achieving a desired wiring density in a given region is a routine design consideration. Doing so would provide a flatter, more bondable surface (Chen, Column 4, lines 49-51).
Re: Claim 2, Uehira, Onuki, and Chen disclose all the limitations of claim 1 on which this claim depends.
Onuki further discloses: a second pattern density (Onuki, wiring density of a wiring pattern; ¶ [0005]), the plurality of wiring layers (Onuki, M wiring layers where M is an integer greater than 1; ¶ [0027], Fig. 1A, element 12), and that each wiring layer includes one or more wiring patterns (Onuki, ¶ [0043]) among the peripheral region (Onuki, Fig. 4, elements 11 and 12).
Onuki is silent regarding:
wherein a pattern density of each of the wiring layers other than the wiring layer closest to the main surface among the plurality of wiring layers in the peripheral region is 30% or less in an arbitrary 100 μm2 region
Chen discloses that the (dummy) pattern density should be less than about 40% (Chen, Column 4, lines 50-51). Pattern density is a known result-effective variable as it can be predicably adjusted to influence stress, load, and bonding strength of the surface (Chen, Column 4, lines 40-50).
A POSITA before the effective filing date would have recognized that adjusting a workable range of pattern densities (40% or less) to a sub-narrower range of the pattern density within the plurality of wiring layers (30% or less) within an arbitrary 100 μm2 given region would have been an obvious matter of routine optimization (MPEP 2144.05, Section II) to achieve predictable results.
Re: Claim 16, Uehira, Onuki, and Chen disclose all the limitations of claim 1 on which this claim depends.
Uehira, Onuki, and Chen disclose:
A device, comprising:
the photoelectric conversion device according to claim 1; Onuki further discloses:
a processor (Onuki, photoelectric conversion apparatus; Fig. 9, element 2000) configured to process a signal outputted (Onuki, signal processing unit; Fig. 9, element 5080) from the photoelectric conversion apparatus.
Onuki discloses that the signal processing unit may have a function of performing AD conversion on the output signal from the photoelectric conversion apparatus (Onuki, ¶ [0087]). A POSITA would have been motivated to incorporate a signal processing unit as a processor for processing an output signal from the photoelectric conversion apparatus (Onuki, ¶ [0087]).
Re: Claim 21: Uehira, Onuki, and Chen disclose all the limitations of claim 1 on which this claim depends.
Uehira further discloses:
wherein a wiring structure (Uehira, second chip, wiring layer; Fig. 16, elements 500 and 300, respectively) including the plurality of wiring layers (Uehira, plurality of wiring layers; ¶ [0067], Fig. 16, element 530 and element 300), is arranged on the main surface (Uehira, front surface; Fig. 16, element 201),
the semiconductor layer (Uehira, semiconductor layer; ¶ [0064], Fig. 16, elements 520 and 200) and the wiring structure constitute a first semiconductor component (Uehira, Fig. 16, everything below region 202 can be considered a first semiconductor component),
the photoelectric conversion apparatus (Uehira, photoelectric conversion device; ¶ [0064], Fig. 1A , element 010 further comprises a second semiconductor component (Uehira, optical layer; Fig. 16, element 400) in contact with the first semiconductor component (Uehira, Fig. 16 shows element 400 on top of element 200, which is a part of the first semiconductor component),
the wiring structure further includes a plurality of conductive portions (Uehira, embedded material; Fig. 16, element 143, ¶ [0071]) in contact with the second semiconductor component.
Claim 3 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1), in view of Onuki (US 2022/0320158 A1), further in view of Chen (US 9.412,725 B2), and further in view of Sekine (US 20230215899 A1).
Re: Claim 3: Uehira, Onuki, and Chen disclose all limitations of Claim 1 on which this claim depends.
Onuki further discloses:
wherein a difference between the pattern density in the wiring patterns arranged in the pixel region among the plurality of wiring patterns and a third pattern density of the wiring patterns arranged in the peripheral region of the plurality of wiring patterns (Onuki, first wiring pattern located in a region aligned with the pixel region has a higher wiring density than the first wiring pattern located in a region aligned with the peripheral region; ¶ [0005]).
Uehira, Onuki, and Chen do not disclose:
wherein a difference between the pattern density in an arbitrary 100 μm2 region of the wiring patterns arranged in the pixel region among the plurality of wiring patterns and a pattern density in an arbitrary 100 μm2 region of the wiring patterns arranged in the peripheral region of the plurality of wiring patterns is 5% or less.
Sekine discloses:
the difference in the density of the conductive part in the wiring layer (Sekine, Fig. 6A, element 621) between the pixel region (Sekine, Fig. 6A, element 601) and peripheral region (Fig. 6A, element 602) can be reduced by introducing mesh-shaped parts (Sekine, Fig. 7C, element 711).
A POSITA before the effective filing date would have recognized that by using the technique taught by Sekine to adjust the different densities in the pixel region and peripheral region, taught by Onuki, the difference between the two regions could be reduced to the claimed 5% or less in an arbitrary 100 μm2 region. Additionally, adjusting the pattern densities in such a manner is a predictable result of optimization within prior art conditions or through routine experimentation (MPEP 2144.05, Section II). Therefore, it would have been obvious to use the disclosure of Sekine to adjust the pattern density difference taught by Onuki to reduce the influence of coupling (Onuki, ¶ [0057]).
Claim 4 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), and further in view of Imai (US 2012/0199382 A1), hereinafter referred to as Uehira, Onuki, Chen, Kagawa and Imai.
Re: Claim 4, Uehira, Onuki, and Chen disclose all limitations of Claim 1 on which this claim depends.
Uehira, Onuki, and Chen are silent regarding:
wherein a plurality of input/output terminals for electrically connecting the photoelectric conversion apparatus and an external device are arranged in the peripheral region,
a plurality of openings for exposing the plurality of input/output terminals are arranged in the semiconductor layer, and in an orthographic projection with respect to the main surface,
the plurality of wiring patterns comprise a first wiring pattern arranged between two adjacent openings in the plurality of openings.
Kagawa discloses a plurality of openings (Kagawa, openings; Fig. 7E, elements 92a, 92b) arranged in the semiconductor layer (Kagawa, Fig. 7E element 20), input/output terminals (Kagawa, electrode pad is an input/terminal; Fig. 2, element 14) used when the photodetection device (Kagawa, Fig. 2, element 1) is electrically connected to an external device (Kagawa, ¶ [0103]). A plurality of the input/output terminals (Kagawa, electrode pads (also called bonding pads), Fig. 2, element 14) are arranged in the peripheral region (Kagawa, Fig. 1, element 2B). Kagawa further discloses that the electrode pad is exposed from a surface (Kagawa, Fig. 5, element S6) of the insulating layer (Kagawa, Fig. 5, element 60) to the outside, where the insulating layer is interposed between the electrode pad and a semiconductor layer.
While Kagawa does not explicitly disclose arranging the plurality of openings to expose the electrode pads, it separately discloses a.) a plurality of openings in the semiconductor layer and b.) exposure of terminals (Kagawa, where a part of the electrode pad is buried in the first semiconductor layer; ¶ [0103]), a POSITA before the effective filing date would be able to combine the disclosure of openings in the semiconductor layer and exposure of the input/output terminals in Kagawa to arrange the openings to expose the electrodes in the semiconductor layer to enable electrical connection to an external circuit. Furthermore,
Kagawa does not disclose:
in an orthographic projection with respect to the main surface, the plurality of wiring patterns comprise a first wiring pattern arranged between two adjacent openings in the plurality of openings.
Imai discloses openings (Imai, Fig.4, element 26) and the plurality of the openings are arranged side by side along an extending direction of the select wiring pattern (Imai, ¶ [0016], Fig. 4, element 22) of which there is a first wiring pattern illustrated between two adjacent openings (Imai, Fig. 4, element 22A). Imai further discloses that “a specific number of the wiring patterns to be disposed can be appropriately changed” (Imai, ¶ [0042]).
Kagawa, as modified by Imai, discloses how to arrange wiring patterns and input/output terminals within a semiconductor layer. A POSITA would be motivated to combine the teachings of these references as coordinating wiring patterns and terminal features in design consideration in semiconductor layers to enable more efficient electrical connections to minimize deterioration (Imai, (¶ [0052]).
Claim 5 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), in further view of Imai (US 2012/0199382 A1), and in further view of Imazu (US 20240352275 A1).
Re: Claim 5, Uehira, Onuki, Chen, Kagawa and Imai disclose all limitations of Claim 4 on which this claim depends.
Uehira, Onuki, Chen, Kagawa are silent regarding:
wherein a distance between each of the two openings and the first wiring pattern is 3 μm or less
Imai further discloses two openings and a first wiring pattern (Imai, Fig. 4; elements 22A and 26). Imai also discloses that the openings are arranged such that intervals between the openings adjacent to each other are substantially equal (Imai, ¶ [0013]).
Imai does not disclose:
a distance between the opening and wiring pattern to be 3 μm or less.
Imazu discloses how to form a metal layer having a wiring pattern with a wiring width of 3 μm or less and an inter-wiring distance of 3 μm or less by electrolytic plating (Imazu, Claim 1). Although Imazu does not explicitly disclose the distance between each of the two openings and wiring pattern to be 3 μm or less, it discloses a minimum spacing between adjacent wiring features. A POSITA before the effective filing date would be able to combine the teaching of openings and wiring patterns in Imai to the inter-wiring distance of Imazu to constrain the distance between features, including openings, to increase the density of wiring and the performance of the semiconductor package (Imazu, ¶ [0002-0003]).
Claim 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), in further view of Imai (US 2012/0199382 A1), and in further view of Sung (KR20220102331A).
Re: Claim 6, Uehira, Onuki, Chen, Kagawa and Imai disclose all limitations of Claim 4 on which this claim depends.
Uehira, Onuki, Chen, Kagawa, and Imai are silent regarding:
wherein the first wiring pattern is a dummy pattern.
Sung discloses layouts of wiring patterns of semiconductors (Sung, Figs. 1A – 1D), with Fig. 1A demonstrating the first wiring pattern to be a dummy pattern (Sung, Fig. 1A, element 10). It would have been obvious to a POSITA before the effective filing date to implement the features as being a predictable design choice in the art within the meaning of KSR v. Teleflex, 550 U. S. 398 (2007).
Claims 7 and 10 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), in further view of Imai (US 2012/0199382 A1), and in further view of Shin (US 7683451 B2).
Re: Claim 7, Uehira, Onuki, Chen, Kagawa and Imai disclose all limitations of Claim 4 on which this claim depends.
Uehira, Onuki, Chen, Kagawa, and Imai are silent regarding:
wherein in the orthographic projection with respect to the main surface, the plurality of wiring patterns includes a second wiring pattern arranged between a first opening arranged to be adjacent to the pixel region among the plurality of openings and the pixel region.
Shin discloses:
in an orthographic projection (plan view) of the main surface, a plurality of wiring patterns (Shin, Fig. 4A, elements 322, 324, 320, 354) and a wiring pattern (Shin, Fig. 3C, element 352) between an opening (Shin. Fig. 3C, element 352a) and the pixel region (Shin, Fig. 4A, element PD) among the plurality of openings (Shin, Fig. 3C). Although Shin does not explicitly label a ‘second wiring pattern’ or a ‘first opening’ it discloses multiple wiring patterns and openings such that a POSITA could identify a wiring pattern adjacent to the opening and pixel region. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels.
Re: Claim 10, Uehira, Onuki, Chen, Kagawa and Imai disclose all limitations of Claim 4 on which this claim depends.
Uehira further discloses that the peripheral region comprises a circuit region (Uehira, peripheral circuit portion; not illustrated, ¶ [0064]), in which a driving circuit for driving the pixel region is arranged (Uehira, circuit element such as a transistor; ¶ [0079]). Uehira discloses a plurality of wiring patterns (Uehira, Fig. 2; element 320). Uehira also discloses “positions and shapes of the respective constituent elements can be freely designed” (Uehira, regarding the peripheral circuit portion; ¶ [0078]).
Uehira, Onuki, Chen, Kagawa and Imai are silent regarding:
a third wiring pattern arranged between a second opening arranged to be adjacent to the circuit region in the plurality of openings and the circuit region.
Shin discloses:
(in plan view), openings (Shin, Fig. 3C, element 352a) and a plurality of wiring patterns (Shin, Fig. 4A, elements 322, 324, 320, 354). Although Shin does not explicitly label a ‘third wiring pattern’ or a ‘second opening’, it discloses multiple wiring patterns and openings such that a POSITA could identify an opening and a wiring pattern for the purposes of arrangement. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels.
Uehira and Shin do not explicitly recite the arranged structure, but Uehira recognizes that that the positions and shapes of the circuit region can be freely designed. A POSITA before the effective filing date would have been motivated to take the teachings of the circuit region in Uehira and combine it with the teachings of wiring patterns and openings in Shin as routine semiconductor design, resulting in the claimed arrangement (MPEP, 2143).
Claims 8 and 11 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), in further view of Imai (US 2012/0199382 A1), in further view of Shin (US 7683451 B2), and in further view of Imazu (US 20240352275 A1).
Re: Claim 8, Uehira, Onuki, Chen, Kagawa, Imai and Shin disclose all limitations of Claim 7 on which this claim depends.
Uehira, Onuki, Chen, Kagawa, Imai are silent regarding:
wherein in the orthographic projection with respect to the main surface, a distance between the first opening and the second wiring pattern is 3 µm or less, and
in the orthographic projection with respect to the main surface, a distance between the pixel region and the second wiring pattern is 3 µm or less.
Shin further discloses:
(in plan view) the opening (Shin, Fig. 3C, element 352a), the pixel region (Shin, Fig. 4A, element PD), a plurality of wiring patterns (Shin, Fig. 4A, elements 322, 324, 320, 354). Although Shin does not explicitly label a ‘second wiring pattern’ or a ‘first opening’ it discloses multiple wiring patterns and openings such that a POSITA could identify a wiring pattern adjacent to the opening and pixel region. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels.
Shin does not teach:
in the orthographic projection with respect to the main surface, a distance between the pixel region and the second wiring pattern is 3 µm or less.
Imazu discloses:
Forming a metal layer having a wiring pattern with a wiring width of 3 μm or less and an inter-wiring distance of 3 μm or less by electrolytic plating (Imazu, ¶ [0014]). Although Imazu does not explicitly disclose that the distance between each of the two openings and wiring pattern to be 3 μm or less, it discloses a minimum spacing between adjacent wiring features. A POSITA before the effective filing date would be able to combine the teachings of pixel region, wirings, and openings from Shin with the spacing taught in Imazu to constrain the distance between features, including openings and regions, to make the device smaller (Imazu, ¶ [0006]).
Re: Claim 11, Uehira, Onuki, Chen, Kagawa, Imai and Shin disclose all the limitations of Claim 10 on which this claim depends.
Uehira further discloses a circuit region (peripheral circuit portion; not illustrated, ¶ [0064]).
Shin further discloses (in plan view) discloses a plurality of wiring patterns (Shin, Fig. 4A, elements 322, 324, 320, 354) and openings (Shin, Fig. 3C, element 352a). Although Shin does not explicitly label a ‘third wiring pattern’ or a ‘second opening’, it discloses multiple wiring patterns and openings such that a POSITA could identify an opening and a wiring pattern for the purposes of arrangement. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels.
Uehira, Onuki, Chen, Kagawa and Imai are silent regarding:
a distance between the second opening and the circuit region and the third wiring pattern is 3 μm or less,
and in the orthographic projection with respect to the main surface, a distance between the circuit region and the third wiring pattern is 3 µm or less.
Imazu discloses how to form a metal layer having a wiring pattern with a wiring width of 3 μm or less and an inter-wiring distance of 3 μm or less by electrolytic plating (Imazu, ¶ [0014]). Although Imazu does not explicitly disclose that the distance between the ‘second’ opening and the circuit region and the third wiring to be 3 μm or less, it discloses a minimum spacing between adjacent wiring features. A POSITA before the effective filing date would be able to combine the teachings of the circuit region and wirings from Uehira with the openings, wiring patterns and openings of Shin with the spacing taught in Imazu to constrain the distance between features, including openings and regions, to make the device smaller (Imazu, ¶ [0006]).
Claims 9 and 12 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Kagawa (US 2024/0175802 A1), in further view of Imai (US 2012/0199382 A1), in further view of Shin (US 7683451 B2), and in further view of Sung (KR20220102331A).
Re: Claim 9, Uehira, Onuki, Chen, Kagawa, Imai and Shin disclose all limitations of Claim 7 on which this claim depends.
Uehira, Onuki, Chen, Kagawa, Imai and Shin are silent regarding:
wherein the second wiring pattern is a dummy pattern
Sung discloses:
layouts of wiring patterns of semiconductors (Sung, Figs. 1A – 1D). Referring to FIG. 1B, a semiconductor device according to an embodiment of the present disclosure may include non-conductive dummy patterns (Sung, Fig. 1B, element 10) and conductive wiring patterns (Sung, Fig. 1B, element 20) alternately arranged in a first horizontal direction (Sung, Fig. 1B, element D1). Although Sung does not explicitly label a ‘second wiring pattern is a dummy pattern” it discloses multiple wiring patterns such that a POSITA could identify a wiring pattern corresponding to a second dummy pattern. It would therefore be obvious to a POSITA before the effective filing date to adjust the teachings of wiring patterns and dummy patterns to the corresponding structure recited.
Re: Claim 12, Uehira, Onuki, Chen, Kagawa, Imai and Shin disclose all limitations of Claim 10 on which this claim depends.
Uehira and Shin are silent regarding:
wherein the third wiring pattern is a dummy pattern
Sung discloses:
layouts of wiring patterns of semiconductors (Sung, Figs. 1A – 1D). Referring to FIG. 1B, a semiconductor device according to an embodiment of the present disclosure may include non-conductive dummy patterns (Sung, Fig. 1B, element 10) and conductive wiring patterns (Sung, Fig. 1B, element 20) alternately arranged in a first horizontal direction (Sung, Fig. 1B, element D1). Although Sung does not explicitly label a ‘third wiring pattern’ as a dummy pattern, it discloses multiple wiring patterns such that a POSITA could identify a wiring pattern corresponding to a third dummy pattern. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels. It would therefore be obvious to a POSITA before the effective filing date to adjust the teachings of wiring patterns and dummy patterns to the corresponding structure recited (Sung, ¶ [0014]).
Claims 13 and 14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1) in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Imai (US 2012/0199382 A1), and in further view of Imazu (US 20240352275 A1).
Re: Claim 13, Uehira, Onuki, and Chen disclose all limitations of Claim 1 on which this claim depends.
Uehira, Onuki, and Chen are silent regarding:
wherein in an orthographic projection with respect to the main surface, the plurality of wiring patterns includes a fourth wiring pattern arranged along the outer edge and in the orthographic projection with respect to the main surface a distance between the outer edge and the fourth wiring pattern is 3 μm or less.
Imai discloses:
a plurality of wiring patterns (Imai, Fig. 5, element 22B) along an outer edge (in plan view), including a fourth wiring pattern. Although Imai does not explicitly label a ‘fourth wiring pattern’, it discloses multiple wiring patterns such that a POSITA could identify a wiring pattern corresponding to a fourth wiring pattern.
Imai does not disclose:
the distance between this edge and the fourth wiring pattern to be 3 μm or less.
Imazu discloses
form a metal layer having a wiring pattern with a wiring width of 3 μm or less and an inter-wiring distance of 3 μm or less by electrolytic plating (Imazu, Claim 1). Although Imazu does not explicitly disclose this distance to be from an edge to a wiring pattern, a POSITA before the effective filing date would be able to use this technique to wire a pattern from another feature (such as: wiring, edge, opening). The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels. Therefore, it would have been obvious to a POSITA to use the teachings of the wiring patterns in Imai and the 3 μm or less distance taught by Imazu to downsize the semiconductor (Imazu, ¶ [0006]).
Re: Claim 14, Uehira, Onuki, Chen, Imai, and Imazu disclose all limitations of Claim 13 on which this claim depends.
Imai further discloses a plurality of wiring patterns (Imai, Figs. 4 – 7, elements 22A + 22B) in which a fourth wiring pattern can be identified to be in contact with an outer edge in an orthographic projection (plan view). The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels. Although Imai does not expressly state “in contact with the outer edge” Fig. 5 (Imai, Fig. 5) shows the wiring pattern touching the edge in the view. A POSITA before the effective filing date would be able to position a wiring pattern so that it is in contact with the outer edge as a predictable arrangement of elements that does not affect their function, to improve flexibility of design (Imai, ¶ [0014]).
Claim 15 is are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1), in view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), in further view of Imai (US 2012/0199382 A1), in further view of Imazu (US 20240352275 A1), and in further view of Sung (KR20220102331A).
Re: Claim 15, Uehira, Onuki, Chen, Imai, and Imazu disclose all limitations of Claim 13 on which this claim depends. Uehira, Onuki, Chen, Imai and Imazu are silent regarding:
wherein the fourth wiring pattern is a dummy pattern
Sung discloses:
configurations of wiring patterns (Sung, Figs. 1A – 1D). Referring to FIG. 1B, a semiconductor device according to an embodiment of the present disclosure may include non-conductive dummy patterns (Sung, Fig. 1B, element 10) and conductive wiring patterns (Sung, Fig. 1B, element 20) alternately arranged in a first horizontal direction (Sung, Fig. 1B, element D1). Although Sung does not explicitly label a ‘fourth wiring pattern’ as a dummy pattern, it discloses multiple wiring patterns such that a POSITA could identify a wiring pattern corresponding to a fourth dummy pattern. The numbering in the claim serves to distinguish elements and does not require the reference to use identical labels. It would therefore be obvious to a POSITA before the effective filing date to adjust the teachings of wiring patterns and dummy patterns to the corresponding structure recited (Sung, ¶ [0014]).
Claim 17 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1), in view of Coult (US 6437868 B1), in further view of Onuki (US 2022/0320158 A1), and in further view of Chen (US 9.412,725 B2).
Re: Independent Claim 17,
Uehira discloses:
a method for manufacturing a photoelectric conversion apparatus (Uehira, manufacturing method of a photoelectric conversion device; ¶ [0001]), the method comprising:
preparing a semiconductor layer (Uehira, preparing a member including a semiconductor layer, Claim 1; Figs. 18 – 23, element 520), in which a plurality of pixels (Uehira, having pixels lined up in a plurality of rows and a plurality of columns; Fig. 2, elements 101, 102, 103), including a photoelectric conversion element are arranged (Uehira, Pixels having a photodiode; ¶ [0002]).
Uehira also discloses a surface on an opposite side to a main surface where a plurality of wiring layers is arranged, an element in which wiring or the like for reading a signal from a pixel is arranged on a surface on an opposite side to a light-receiving surface (Uehira, wiring or the like for reading a signal from a pixel is arranged on a surface on an opposite side to a light-receiving surface of a semiconductor layer; ¶ [0002]). Uehira further discloses a plurality of wiring patterns (Uehira, plurality of wirings; Fig. 2, element 320) are arranged in a wiring layer (Uehira, wiring layer; Fig. 2, element 300) closest to the main surface among the plurality of wiring layers (Uehira, plurality of wiring layers; Fig. 2, i.e. element 530).
Uehira is silent regarding:
thinning the semiconductor layer from a side of a light receiving surface on an opposite side to a main surface where a plurality of wiring layers are arranged,
wherein a plurality of wiring patterns are arranged in a wiring layer closest to the main surface among the plurality of wiring layers,
Coult discloses:
thinning (Coult, chemical mechanical polishing (CMP), Column 1, lines 20-37) the semiconductor layer (Coult, workpiece; Fig. 1, element 120) from a side of a light receiving surface (Coult, chuck face; Fig. 1, element 114, the top surface of element 114 can be considered a side of a light receiving surface) on an opposite side to a main surface (Coult, Fig. 1, the bottom portion of 120 and the top portion of the rotating table, element 124 can be considered a main surface) where a plurality of wiring layers (Coult, control lines; drive, Figs. 1 and 6, elements 404, 406, and 702, respectively, Col.5, lines 17-21, collectively can make up a plurality of wiring layers) are arranged,
wherein a plurality of wiring patterns (Coult, control lines; Fig. 6, elements 404 and 406 Col.5, lines 17-21, can make up a plurality of wiring patterns) are arranged in a wiring layer (Coult, workpiece; Fig. 6, element 120 contains some control lines and therefore can be considered a wiring layer) closest to the main surface among the plurality of wiring layers,
A POSITA before the effective filing date would have been motivated to combine the technique of thinning to the semiconductor and wiring layers disclosed by Coult for a semiconductor workpiece to the semiconductor layer of Uehira because thinning a semiconductor and measuring in-situ is a well-known step to achieve desired thickness without damaging the semiconductor layer (Coult, Column 1, lines 53-55).
Uehira, as modified by Coult, does not disclose:
and a pattern density of the wiring patterns arranged in a peripheral region between the pixel region and an outer edge of the semiconductor layer among the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region.
Onuki discloses a pattern density (Onuki, wiring density of a wiring pattern; ¶ [0005]) of the wiring patterns (Onuki, wiring layer including one or more wiring patterns; ¶ [0043]) arranged in a peripheral region (Onuki, peripheral region; Fig. 5A, element 102) between the pixel region (Onuki, pixel region; element 100, Fig. 5A) and an outer edge of the semiconductor layer (Onuki, semiconductor element layer; Fig. 4, element 11). Onuki further discloses that the first wiring pattern located in a region aligned with the pixel region has a higher wiring density than the wiring pattern aligned with the peripheral region (Onuki, ¶ [0005]). It would have been obvious to a POSITA before the effective filing date of the claimed invention to include the modifications of wiring density in the peripheral region taught by Onuki to the peripheral circuit region of Uehira, modified by Coult to include the thinning technique of the semiconductor layer, to reduce impedance and influence of coupling due to potential fluctuations (Onuki, ¶ [0065]) and prevent damage to the semiconductor layer (Coult, Column 1, lines 53-55).
Uehira, as modified by Coult and Onuki, still fails to disclose:
the plurality of wiring patterns is 35% or more in an arbitrary 100 μm2 region of the peripheral region.
Chen discloses that the numerical pattern density or 40% or less (Chen, Column 4, lines 50-51), though only for a dummy pattern. The density taught by dummy patterns is directly applicable to wiring patterns, as both occupy patterned areas within the wiring layer. It would have been obvious to a POSITA before the effective filing date of the claimed invention to select a wiring pattern density (which can include dummy and functional patterns) within the 35% – 40% range in an arbitrary 100 μm2 region of the peripheral region, since achieving a desired wiring density in a given region is a routine design consideration. Doing so would provide a flatter, more bondable surface (Chen, Column 4, lines 49-51).
Coult further discloses:
that in the thinning (Coult, chemical mechanical polishing (CMP), Column 1, lines 20-37) a film thickness of the semiconductor layer including the peripheral region (Coult, workpiece; Fig. 1, element 120, the surrounding region can be considered the peripheral region) is measured by using reflected light of light irradiated onto the light receiving surface (Coult, a method for measuring the thickness of a workpiece, measuring the time of arrival of at least one reflected optical signal from the top of said workpiece; measuring the time of arrival of at least one reflected optical signal from the bottom of said workpiece; determining the thickness of said workpiece by calculating the difference between the time of arrival of said reflected signals; and continuing the thinning operation until the desired thickness is reached, Column 6, Claim 24).
A POSITA before the effective filing date would have been motivated to combine the technique of thinning and measuring thickness simultaneously taught by Coult for a semiconductor workpiece including the peripheral region to the semiconductor layer including the peripheral region of Uehira because thinning a semiconductor and measuring in-situ is a well-known step to achieve desired thickness without damaging the semiconductor layer (Coult, Column 1, lines 53-55).
Claims 18 – 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Uehira (US 2022/0406835 A1), in view of Coult (US 6437868 B1), in further view of Onuki (US 2022/0320158 A1), in further view of Chen (US 9.412,725 B2), and in further view of Yoshihara (US 20140306313 A1).
Re: Claim 18, Uehira, Coult, Onuki, and Chen disclose all limitations of Claim 17 on which this claim depends.
Uehira further discloses:
wherein in the preparing, a plurality of pixel regions including the pixel region are arranged in the semiconductor layer (Uehira, preparing a member including 1) a semiconductor layer, claim 1; Figs. 18 – 23, element 520), in which a plurality of pixels (Uehira, having pixels lined up in a plurality of rows and a plurality of columns; Fig. 2, elements 101, 102, 103).
Uehira, Coult, Onuki, and Chen are silent regarding:
the method further comprises cutting the semiconductor layer in a scribe region, and dicing into chips each comprising a pixel region, and prior to the dicing, the plurality of wiring patterns includes a wiring pattern arranged in the scribe region.
Yoshihara discloses:
cutting the semiconductor layer in a scribe region (Yoshihara, a wafer state before dicing; ¶ [0105], the scribe areas (Yoshihara, Fig. 13, elements LA1 and LA2), and dicing into chips (Yoshihara, the first semiconductor chip; Fig. 13, element 100) is each comprising a pixel region (Yoshihara, provided with the pixel area; Fig. 3, element PA), and prior to the dicing the plurality of wiring patterns includes a wiring pattern arranged in the scribe region (Yoshihara, as shown in FIG. 36, the etching process is performed on the scribe areas of the plurality of semiconductor chips so as to expose the surface of the pad electrode (Yoshihara, Fig. 12, element PAD1) connected to the wiring portions (Yoshihara, Fig. 36, element 111hc, ¶ [0105]). In the method steps recited in the spec. of Yoshihara, etching (step e) comes prior to dicing (step g) (Yoshihara, ¶ [0314] - ¶ [0325]).
It would be obvious to a POSITA to combine the cutting method in the scribe region of the semiconductor layer described by Yoshihara to the semiconductor layer described by Uehira to arrange chip and circuits to achieve higher apparatus functionality (Yoshihara, ¶ [0006 – 0007]).
Re: Claim 19, Uehira, Coult, Onuki, Chen and Yoshihara disclose all limitations of Claim 18 on which this claim depends.
Onuki further discloses:
a fourth pattern density (Onuki, wiring density of a wiring pattern; ¶ [0005]) of the wiring patterns (Onuki, each wiring layer includes one or more wiring patterns; ¶ [0043]).
Onuki does not disclose:
wherein prior to the dicing, a fourth pattern density of the wiring pattern arranged in the scribe region among the plurality of wiring patterns
Yoshihara discloses the semiconductor layer in a scribe region (Yoshihara, a wafer state before dicing; ¶ [0105], the scribe areas (Yoshihara, Fig. 13, elements LA1 and LA2), and wiring portions in the scribe area (Yoshihara, Fig. 13, elements 211h and 211z).
Onuki, further modified by Yoshihara does not explicitly disclose:
wiring pattern arranged in the scribe region among the plurality of wiring patterns. However, it would have been obvious to a POSITA to use the wiring pattern density of Onuki in the scribe region describe by Yoshihara, as scribe lines are routinely used for testing to avoid using more active die area.
Furthermore, Onuki, as modified by Yoshihara does not disclose:(the density of these) patterns is 35% or more in an arbitrary 100 μm2 region.
Chen discloses the numerical pattern density or 40% or less (Chen, Column 4, lines 50-51), though only for a dummy pattern. The density taught by dummy patterns is directly applicable to wiring patterns, as both occupy patterned areas within the wiring layer. It would have been obvious to a POSITA before the effective filing date of the claimed invention to select a wiring pattern density (which can include dummy and functional patterns) within the 35% – 40% range in an arbitrary 100 μm2 region of the peripheral region, since achieving a desired wiring density in a given region is a routine design consideration. Doing so would provide a flatter, more bondable surface (Chen, Column 4, lines 49-51).
Re: Claim 20, Uehira, Coult, Onuki, Chen and Yoshihara disclose all limitations of Claim 18 on which this claim depends.
Yoshihara further discloses:
prior to the dicing, the plurality of wiring patterns (Yoshihara, plurality of wiring portions; Fig. 4, element 111h, 111z) includes a wiring pattern arranged to straddle adjacent chips (Yoshihara, each semiconductor chip includes a wiring portion, the wiring portions are electrically connected to each other through the conductive layer (Yoshihara, Fig. 19, element 401), ¶ [0028]). It would therefore be obvious for a POSITA to use the technique of Yoshihara to arrange adjacent chips electrically for a high-function apparatus (Yoshihara, ¶ [0007]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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/NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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