DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weindorf et al. Publication No. US 2005/0057874.
Regarding claim 16, Weindorf discloses a circuit, comprising:
a first transistor [Fig 1, transistor 14] having a first control input [Fig. 1, gate of the transistor 14], a first current terminal [Fig. 1, drain of the transistor 14], and a second current terminal [Fig. 1, source of 14], the second current terminal coupled to a supply reference terminal [Fig. 1, source of 14 is coupled to a ground via resistor 18];
a first resistor [Fig. 1, resistor 28] coupled between a first voltage input [Fig. 1, 26] and the first control input [Fig. 1, resistor 28 is coupled between 26 and the gate of the transistor 14]; and
a second transistor [Fig. 1, transistor 20] having a second control input [Fig. 1, gate of 20] and a third current terminal [Fig. 1, collector of transistor 20], the second control input coupled to a second voltage input [Fig. 1, the gate of the transistor 20 is coupled to the output voltage at 16], and the third current terminal coupled to the first control input [Fig. 1, collector terminal of 20 is coupled to the gate of 14].
Regarding claim 17, Weindorf further comprises a resistor divider [Fig. 1, voltage divider comprising resistors 22, 24] coupled between the second voltage input and the supply reference terminal [Fig.1, coupled between the output voltage at 16 and ground 34], the resistor divider having an output coupled to the second control input [Fig. 1, the output of the voltage divider is coupled to the gate of the transistor 20].
Regarding claim 20, Weindorf discloses that the second transistor has a fourth current terminal coupled to the supply reference terminal [Fig. 1, the emitter terminal of the second transistor 20 is coupled to the ground 34].
Allowable Subject Matter
Claims 18-19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 18: The prior art does not further comprise a third transistor coupled between the first voltage input and the first resistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 21: The prior art does not disclose a current inrush limiting circuit having an input and output, the input of the current inrush limiting circuit coupled to the third control input, and the output of the current inrush limiting circuit coupled to the first current terminal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Claims 1-15 are allowed.
The following is an examiner’s statement of reasons for allowance of claim 1: The prior art by Kim et al. Publication No. US 2021/0376596 discloses an apparatus, comprising:
a transistor [Fig. 4, transistor Q1] having a first control input [gate G of the transistor] and a first current terminal [drain/source of the transistor];
a controller [Fig. 1, mode controller 120] having a controller output coupled to the first control input [Fig. 4, the output of the comparator U1 is coupled to the gate of the transistor Q1];
a current inrush limiting circuit [Fig. 4, inrush current limiter 110] having an input and output, the input of the current inrush limiting circuit coupled to the first control input [Fig. 4, the input of the ICL 110 is electrically coupled to the gate of the transistor Q1].
However, the prior art does not disclose a disable circuit having a first input, a sense input, and a supply reference terminal, the first input of the disable circuit coupled to the output of the current inrush limiting circuit, the sense input coupled to the first current terminal, and the disable circuit configured to: in response to a voltage of the first current terminal being below a threshold, couple the output of the current inrush limiting circuit to the supply reference terminal; and in response to the voltage of the first current terminal being above the threshold, decouple the output of the current inrush limiting circuit from the supply reference terminal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 10: The prior art by Kim et al. Publication No. US 2021/0376596 discloses a power control circuit, comprising:
a first transistor [Fig. 4, Q1] having a first control input and a first current terminal;
a controller [Fig. 4, mode controller 120] having a controller output coupled to the first control input;
a second transistor [Fig. 4, SW1] having a second control input and second and third current terminals, the third current terminal coupled to a supply reference terminal [Fig. 4, the bottom terminal of the switch SW1 is coupled to the ground];
a current inrush limiting circuit [Fig. 4, current inrush limiter 110] having an input and output, the input of the current inrush limiting circuit coupled to the first control input, and the output of the current inrush limiting circuit coupled to the second current terminal.
However, the prior art does not disclose a first resistor coupled between a voltage input of the power control circuit and the second control input; and a third transistor having a third control input and a fourth current terminal, the third control input coupled to the first current terminal, and the fourth current terminal coupled to the second control input. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/ Primary Examiner, Art Unit 2838