CTFR 18/450,575 CTFR 81235 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 16-17 and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Meier et al. US Patent No. 6,094,040 . Regarding claim 16 , Meier discloses a circuit, comprising: a first transistor [Fig 1, transistor 42] having a first control input [Fig. 1, gate of the transistor 42], a first current terminal [Fig. 1, collector of the transistor 42], and a second current terminal [Fig. 1, emitter of the transistor 42], the second current terminal shorted to a supply reference terminal [Fig. 1, emitter terminal of 42 is shorted to ground as shown]; a first resistor [Fig. 1, resistor 36] coupled between a first voltage input [Fig. 1, B] and the first control input [Fig. 1, resistor 36 is coupled between B and the gate of the transistor 42]; and a second transistor [Fig. 1, transistor 30] having a second control input [Fig. 1, gate of 30] and a third current terminal [Fig. 1, top/drain terminal of transistor 30], the second control input coupled to a second voltage input [Fig. 1, the gate of the transistor 30 is coupled to the output voltage at node 34], and the third current terminal coupled to the first control input [Fig. 1, top/drain terminal of 30 is electrically coupled to the gate of 42]. Regarding claim 17 , Meier further comprises a resistor divider [Fig. 1, voltage divider comprising resistors 26, 28] coupled between the second voltage input and the supply reference terminal [Fig.1, coupled between the voltage at A and ground], the resistor divider having an output coupled to the second control input [Fig. 1, the output of the voltage divider is coupled to the gate of the transistor 30]. Regarding claim 20 , Meier discloses that the second transistor has a fourth current terminal coupled to the supply reference terminal [Fig. 1, the bottom/source terminal of transistor 30 is coupled to the ground] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 18-19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance of claim 18: The prior art does not further comprise a third transistor coupled between the first voltage input and the first resistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 21: The prior art does not disclose a current inrush limiting circuit having an input and output, the input of the current inrush limiting circuit coupled to the third control input, and the output of the current inrush limiting circuit coupled to the first current terminal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. 12-151-07 AIA 07-97 12-51-07 Claim s 1-15 are allowed. The following is an examiner’s statement of reasons for allowance of claim 1: The prior art by Kim et al. Publication No. US 2021/0376596 discloses an apparatus, comprising: a transistor [Fig. 4, transistor Q1] having a first control input [gate G of the transistor] and a first current terminal [drain/source of the transistor]; a controller [Fig. 1, mode controller 120] having a controller output coupled to the first control input [Fig. 4, the output of the comparator U1 is coupled to the gate of the transistor Q1]; a current inrush limiting circuit [Fig. 4, inrush current limiter 110] having an input and output, the input of the current inrush limiting circuit coupled to the first control input [Fig. 4, the input of the ICL 110 is electrically coupled to the gate of the transistor Q1]. However, the prior art does not disclose a disable circuit having a first input, a sense input, and a supply reference terminal, the first input of the disable circuit coupled to the output of the current inrush limiting circuit, the sense input coupled to the first current terminal, and the disable circuit configured to: in response to a voltage of the first current terminal being below a threshold, couple the output of the current inrush limiting circuit to the supply reference terminal; and in response to the voltage of the first current terminal being above the threshold, decouple the output of the current inrush limiting circuit from the supply reference terminal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 10: The prior art by Kim et al. Publication No. US 2021/0376596 discloses a power control circuit, comprising: a first transistor [Fig. 4, Q1] having a first control input and a first current terminal; a controller [Fig. 4, mode controller 120] having a controller output coupled to the first control input; a second transistor [Fig. 4, SW1] having a second control input and second and third current terminals, the third current terminal coupled to a supply reference terminal [Fig. 4, the bottom terminal of the switch SW1 is coupled to the ground]; a current inrush limiting circuit [Fig. 4, current inrush limiter 110] having an input and output, the input of the current inrush limiting circuit coupled to the first control input, and the output of the current inrush limiting circuit coupled to the second current terminal. However, the prior art does not disclose a first resistor coupled between a voltage input of the power control circuit and the second control input; and a third transistor having a third control input and a fourth current terminal, the third control input coupled to the first current terminal, and the fourth current terminal coupled to the second control input. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Response to Arguments Applicant’s arguments with respect to claim(s) 16, 17, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. A new reference by Meier et al. has been introduced to meet the claim limitations of claims 16, 17, and 20 as shown above. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 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To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/ Primary Examiner, Art Unit 2838 Application/Control Number: 18/450,575 Page 2 Art Unit: 2838 Application/Control Number: 18/450,575 Page 3 Art Unit: 2838 Application/Control Number: 18/450,575 Page 4 Art Unit: 2838 Application/Control Number: 18/450,575 Page 5 Art Unit: 2838
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