Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/27/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-11, 13-18, 22, and 24-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (Pub. No.: US 2020/0051907 A1).
Regarding Claim 1, Kang et al. discloses a package substrate, comprising: a first metallization layer extending in a first direction, the first metallization layer comprising: a first surface and a second surface opposite the first surface in a second direction orthogonal to the first direction (Par. 0106-0119; Figs. 10A-10F); a first metal layer adjacent to the first surface, the first metal layer, comprising a plurality of first metal interconnects (Par. 0044; 0106-0119; Figs. 10A-10F – first metal interconnect comprising #323a (embedded interconnect) and #325a (interconnect); first metal layer denoted as red solid rectangle in annotated Fig. 10E below)); and
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a first insulating layer, comprising: a first metal pad layer, comprising: a plurality of first metal pads each in contact with a first metal interconnect of the plurality of first metal interconnects (Par. 0044, 0106- 0119; Figs. 10A-10F; (Fig. 6B – first metal pad 603); see annotated Fig. 10E above); and a plurality of first vias adjacent to the second surface and each in contact with a first metal pad of the plurality of first metal pads (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above) – only one first via is shown but it is understood that there are plurality of them in the structure); wherein the first metal pad layer is disposed between the first metal layer and the plurality of first vias in the second direction, and wherein the plurality of first vias do not directly contact the plurality of first metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above)).
Regarding Claim 2, Kang et al., as applied to claim 1. discloses
the package substrate, wherein the first metal layer is at least partially embedded in the first insulating layer, and the plurality of first metal interconnects comprises a plurality of first embedded metal traces embedded in the first insulating layer (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above) - first insulating layer comprising dielectric layer 324).
Regarding Claim 3, Kang et al., as applied to claim 2. discloses
the package substrate, further comprising:
a second metallization layer extending in the first direction and coupled to the first metallization layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below)), the second metallization layer comprising: a third surface and a fourth surface opposite the third surface in the second direction (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below)); a second insulating layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below) – second insulating layer 326); a second metal layer at least partially embedded in the second insulating layer and adjacent to the third surface, the second metal layer comprising a plurality of second embedded metal traces embedded in the second insulating layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below)); and
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the second insulating layer, comprising: a second metal pad layer, comprising: a plurality of second metal pads each in contact with a second embedded metal trace of the plurality of second embedded metal traces (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)); and a plurality of second vias adjacent to the fourth surface and each in contact with a second metal pad of the plurality of second metal pads (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)); wherein: the plurality of first vias are each coupled to a second embedded metal trace of the plurality of second embedded metal traces (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)).
Regarding Claim 9, Kang et al., as applied to claim 1. discloses
the package substrate, wherein :the plurality of first metal interconnects has a first pitch in the first direction; and the plurality of first metal pads has a second pitch equal to the first pitch in the first direction (Par. 0034, 0045; Figs. 10A-10F (also see annotated Fig. 10E above) – first metal interconnects and first metal pads both seem to be irregularly spaced – some of the first metal pads seem to be as closely packed as the first metal interconnects are) .
Regarding Claim 10, Kang et al., as applied to claim 1. discloses
the package substrate, wherein the plurality of first metal interconnects has a first pitch in the first direction less than or equal to one hundred (100) micrometers (µm) (Par. 0034).
Regarding Claim 11, Kang et al., as applied to claim 1. discloses
the package substrate, wherein the plurality of first metal interconnects has a first pitch in the first direction less than or equal to eighty (80) micrometers (µm) (Par. 0034).
Regarding Claim 13, Kang et al., as applied to claim 1. discloses
the package substrate, wherein: each first metal interconnect of the plurality of first metal interconnects is separated from an adjacent first metal interconnect of the plurality of first metal interconnects by a first distance; each first metal pad of the plurality of first metal pads is separated from an adjacent first metal pad of the plurality of first metal pads by a second distance greater than the first distance (see annotated Fig 10E above).
Regarding Claim 14, Kang et al., as applied to claim 1. discloses
the package substrate, further comprising: a second metallization layer extending in the first direction and coupled to the first metallization layer (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above), the second metallization layer comprising: a third surface and a fourth surface opposite the third surface in the second direction (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above); a second metal layer adjacent to the third surface (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above), the second metal layer comprising a plurality of second metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above); and
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a second insulating layer (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above), comprising: a second metal pad layer (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above), comprising: a plurality of second metal pads each in contact with a second metal interconnect of the plurality of second metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above); and a plurality of second vias adjacent to the fourth surface and each in contact with a second metal pad of the plurality of second metal pads (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above); wherein: the plurality of first vias are each coupled to a second metal interconnect of the plurality of second metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above).
Regarding Claim 15, Kang et al., as applied to claim 1. discloses
the package substrate, wherein the first metal layer further comprises one or more second metal interconnects each disposed between two (2) first metal interconnects of the plurality of first metal interconnects in the first direction (see annotated Fig 10E attached below) .
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Regarding Claim 16, Kang et al., as applied to claim 15. discloses
the package substrate, wherein each of the one or more second metal interconnects is not coupled to a first metal pad of the plurality of first metal pads (see annotated Fig 10E above).
Regarding Claim 17, Kang et al., as applied to claim 1. discloses
the package substrate integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (Par. 0144).
Regarding Claim 18, Kang et al. discloses a method of fabricating a package substrate, comprising: forming a first metallization layer extending in a first direction, the first metallization layer comprising: a first surface and a second surface opposite the first surface in a second direction orthogonal to the first direction (Par. 0106-0119; Figs. 10A-10F); a first metal layer adjacent to the first surface, the first metal layer, comprising a plurality of first metal interconnects (Par. 0044; 0106-0119; Figs. 10A-10F – first metal interconnect comprising #323a (embedded interconnect) and #325a (interconnect); first metal layer denoted as red solid rectangle in annotated Fig. 10E below)); and
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a first insulating layer, comprising: a first metal pad layer, comprising: a plurality of first metal pads each in contact with a first metal interconnect of the plurality of first metal interconnects (Par. 0044, 0106- 0119; Figs. 10A-10F; (Fig. 6B – first metal pad 603); see annotated Fig. 10E above); and a plurality of first vias adjacent to the second surface and each in contact with a first metal pad of the plurality of first metal pads (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above) – only one first via is shown but it is understood that there are plurality of them in the structure); wherein the first metal pad layer is disposed between the first metal layer and the plurality of first vias in the second direction, and wherein the plurality of first vias do not directly contact the plurality of first metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above)).
Regarding Claim 22, Kang et al., as applied to claim 18. discloses
the package substrate, further comprising forming one or more second metal interconnects between two (2) first metal interconnects of the plurality of first metal interconnects in the first direction; wherein each of the one or more second metal interconnects is not coupled to a first metal pad of the plurality of first metal pads (see annotated Fig 10E above) .
Regarding Claim 24, Kang et al. discloses an integrated circuit (IC) package, comprising: a package substrate, comprising: a first metallization layer extending in a first direction, the first metallization layer comprising: a first surface and a second surface opposite the first surface in a second direction orthogonal to the first direction (Par. 0106-0119; Figs. 10A-10F & Fig. 3); a first metal layer adjacent to the first surface, the first metal layer comprising a plurality of first metal interconnects (Par. 0044, 0106-0119; Figs. 10A-10F & Fig. 3 – first metal interconnect comprising #323a (embedded interconnect) and #325a (interconnect); first metal layer denoted as red solid rectangle in annotated Fig. 10E below)); and
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a first insulating layer, comprising: a first metal pad layer, comprising: a plurality of first metal pads each in contact with a first metal interconnect of the plurality of first metal interconnects (Par. 0106-0119; Figs. 10A-10F & Fig. 3) – Par. 0044, 0106- 0119; Figs. 10A-10F; (Fig. 6B – first metal pad 603); see annotated Fig. 10E above); and a plurality of first vias adjacent to the second surface and each in contact with a first metal pad of the plurality of first metal pads (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above) – only one first via is shown but it is understood that there are plurality of them in the structure); wherein the first metal pad layer is disposed between the first metal layer and the plurality of first vias in the second direction, and wherein the plurality of first vias do not directly contact the plurality of first metal interconnects (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above)); and
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a die comprising a plurality of die interconnects each coupled to a first metal interconnect of the plurality of first metal interconnects (Par. 0039-0045; Figs. 10A-10F & Fig. 3 – die 204; die interconnects 240).
Regarding Claim 25, Kang et al., as applied to claim 24, at least implicitly discloses
the IC package, wherein a capacitor is coupled to at least one first metal interconnect of the plurality of first metal interconnects (Par. 0144; Figs. 3, 14 etc. – not mentioned explicitly but implied).
Regarding Claim 26, Kang et al., as applied to claim 25, at least implicitly discloses
the IC package, wherein the capacitor is coupled to the at least one first metal interconnect by the capacitor being coupled to at least one first via of the plurality of first vias (Par. 0144; Figs. 3, 14 etc. – not mentioned explicitly but implied – even if the capacitor is not directly coupled to the first via, it is at least indirectly coupled).
Regarding Claim 27, Kang et al., as applied to claim 24. discloses
the IC package, wherein the first metal layer is at least partially embedded in the first insulating layer, and the plurality of first metal interconnects comprises a plurality of first embedded metal traces embedded in the first insulating layer (Par. 0106-0119; Figs. 10A-10F (see annotated Fig. 10E above) - first insulating layer comprising dielectric layer 324)
Regarding Claim 28, Kang et al., as applied to claim 27, discloses
the IC package, wherein the package substrate further comprises:
a second metallization layer extending in the first direction and coupled to the first metallization layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below)), the second metallization layer comprising: a third surface and a fourth surface opposite the third surface in the second direction (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E below));
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a second insulating layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above) – second insulating layer 326); a second metal layer at least partially embedded in the second insulating layer and adjacent to the third surface, the second metal layer comprising a plurality of second embedded metal traces embedded in the second insulating layer (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)); and the second insulating layer, comprising: a second metal pad layer, comprising: a plurality of second metal pads each in contact with a second embedded metal trace of the plurality of second embedded metal traces (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)); and a plurality of second vias adjacent to the fourth surface and each in contact with a second metal pad of the plurality of second metal pads (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)); wherein: the plurality of first vias are each coupled to a second embedded metal trace of the plurality of second embedded metal traces (Par. 0106-0119; Figs. 10A-10F (also see annotated Fig. 10E above)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12 and 34-35 are rejected under 35 U.S.C. 103 as obvious over Kang et al. (Pub. No.: US 2020/0051907 A1), as applied to claim 1 and claim 24.
Regarding Claim 12, Kang et al., as applied to claim 9, does not explicitly disclose
the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction, the first width being at least fifteen (15) micrometers (µm) greater than the second width. However, Kang et al. teaches
the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction (Par. 0034 – this prior art teaches “each embedded interconnect from the plurality of embedded interconnects 223 has a minimum width of 5 micrometers (μm), and a minimum spacing between embedded interconnects of 5 micrometers (μm)” leaving open the possibilities the width of the first metal pad maybe different and/or less than the width of the first metal interconnect depending on the specific need). Kang et al. discloses the claimed invention except for the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction, the first width being at least fifteen (15) micrometers (µm) greater than the second width. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction, the first width being at least fifteen (15) micrometers (µm) greater than the second width, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Regarding Claim 34, Kang et al., as applied to claim 1, does not explicitly disclose
the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction. However, Kang et al. teaches
the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction (Par. 0034 – this prior art teaches “each embedded interconnect from the plurality of embedded interconnects 223 has a minimum width of 5 micrometers (μm), and a minimum spacing between embedded interconnects of 5 micrometers (μm)” leaving open the possibilities the width of the first metal pad maybe different and/or less than the width of the first metal interconnect depending on the specific need). Kang et al. discloses the claimed invention except for the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the package substrate, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Regarding Claim 35, Kang et al., as applied to claim 24, does not explicitly disclose
the IC package, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction. However, Kang et al. teaches
the IC package, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width in the first direction (Par. 0034 – this prior art teaches “each embedded interconnect from the plurality of embedded interconnects 223 has a minimum width of 5 micrometers (μm), and a minimum spacing between embedded interconnects of 5 micrometers (μm)” leaving open the possibilities the width of the first metal pad maybe different and/or less than the width of the first metal interconnect depending on the specific need). Kang et al. discloses the claimed invention except for the IC package, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the IC package, wherein the plurality of first metal interconnects each have a first width in the first direction, and the plurality of first metal pads each have a second width less than the first width in the first direction, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Response to Arguments
Applicants’ arguments filed on 08/27/2026 have been fully considered but they are moot because of the new grounds of rejection necessitated by amendments made to the claims.
Conclusion
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09/14/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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