DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Abstract
The abstract of the disclosure is objected to because:
Claims of invention contain "A method, claim 21". Please, revise.
A corrected abstract of the disclosure is required and must be presented on a
separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-15, and 18-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster et al. (U.S. 2012/0320558) in view of Muranaga (U.S. Patent 8,199,527).
As to claim 1, Foster discloses an electronic device (20) as shown in figure 5 comprising:
a circuit board (14) coupled to the electronic device (12);
a circuit board component (the outer component 12 formed outside the shielding structure 18) coupled to the circuit board via an under-fill material; and
a material contaminant shield (18) coupled to the circuit board (14) between the circuit board component (12) and the electronic device (12), and wherein the material contaminant shield (18) comprises a wall (not label, para-0049) comprising one or more pick-and-place features (112).
Foster does not specifically disclose the circuit board component coupled to the circuit board via an underfill material, wherein the material contaminant shield is configured to prevent the under-fill material from the circuit board component from contaminating the electronic device.
Muranaga teaches the circuit board component (5) coupled to the circuit board (1) via an underfill material (8), wherein the material contaminant shield is configured to prevent the under-fill material from the circuit board component from contaminating the electronic device.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Muranaga employed in the electronic device of Foster in order to prevent solder slash and short circuit for the chip or component mounted on the circuit board.
Regarding claim 2, Foster as modified by Muranaga discloses the material contaminant shield (18) is configured to prevent the under-fill material from the circuit board component (5 of Muranaga) from contaminating the electronic device through wicking and prevent the under-fill material from the circuit board component from contaminating the electronic device through spattering.
Regarding claim 3, Foster as modified by Muranaga discloses the material contaminant shield (18) has a height sufficient to prevent the under-fill material from the circuit board component (element 5 of Muranaga) from contaminating the electronic device.
Regarding claim 5, Foster as modified by Muranaga discloses the material contaminant shield (18) comprises a plurality of walls (para-0049+), wherein the material contaminant shield comprises a partial lid (112) that extends in a direction away from a first wall of the plurality of walls and towards the electronic device (12).
Regarding claim 6, Foster as modified by Muranaga further comprising one or more electronic components (12), wherein the one or more electronic components are disposed under the partial lid (112).
Regarding claim 7, Foster as modified by Muranaga discloses the material contaminant shield (18) comprises one or more walls (para-0049+), wherein the material contaminant shield (18) comprises a tab (the second element 112 formed in the second compartment 110) that extends from a first wall of the one or more walls in a direction away from the electronic device.
Regarding claim 8, Foster as modified by Muranaga discloses the material contaminant shield (18) is coupled to the circuit board (14) via a solder, para-0046.
Regarding claim 9, Foster as modified by Muranaga discloses the material contaminant shield (18) is configured to provide electromagnetic interference shielding (para-0008+) to the electronic device (12).
Regarding claim 10, Foster as modified by Muranaga discloses the electronic device (12) comprises a crystal oscillator (radio-frequency bands component, para-0040).
Regarding claims 11-12, Foster as modified by Muranaga discloses the electronic device is a capacitor or gyroscope (12, para-0040).
As to claim 13, Foster discloses a shielded oscillator system (20) as shown in figure 5, comprising:
a crystal oscillator (radio-frequency bands 12, para-0040) configured to generate a clock signal; and
a material contaminant shield (18) surrounding the crystal oscillator (12), wherein the material contaminant shield (18) comprises a first wall (para-0049) having a first thickness, wherein the first wall is disposed between the crystal oscillator (12) and a circuit board component (the outside component 12), and wherein the material contaminant shield (18) comprises a second wall (top wall) having one or more pick-and-place features (112) extending in a direction away from the second wall.
Foster does not specifically disclose the material contaminant shield is configured to prevent an under-fill material applied at a location outside of the material contaminant shield from contaminating the crystal oscillator
Muranaga teaches the circuit board component (5) coupled to the circuit board (1) via an underfill material (8), so that the material contaminant shield is configured to prevent the under-fill material from the circuit board component from contaminating the electronic device.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Muranaga employed in the electronic device of Foster in order to prevent solder slash and short circuit for the chip or component mounted on the circuit board.
Regarding claim 14, Foster as modified by Muranaga discloses the one or more pick-and-place features (112) are disposed on opposing sides of the material contaminant shield (18).
Regarding claim 15, Foster as modified by Muranaga discloses the one or more pick-and-place features (112) are on adjected sides of the material contaminant shield.
16. (Original) The shielded oscillator system of claim 13, wherein a height of the first wall is less than 0.7 mm.
Regarding claim 18, Foster as modified by Muranaga discloses the one or more pick-and-place features (112 in a first compartment 110) extend towards the crystal oscillator.
Regarding claim 19, Foster as modified by Muranaga discloses the one or more pick-and-place features (the element 112 on the second compartment 110 that do not cover the element 112 in the first compartment 110) do not cover the crystal oscillator.
Regarding claim 20, Foster as modified by Muranaga discloses the one or more pick-and-place features (112) comprise a tab extending from the second wall (top wall) in a direction away from the crystal oscillator.
As best understood to claim 21, Foster discloses a method (for making an electronic device), as shown in figure 5 comprising:
providing a material contaminant shield system (20 having shielding can or layer), wherein the material contaminant shield system comprises a plurality of walls (para-0049+) and a pick-and-place feature (112) on a first wall of the plurality of walls;
providing the material contaminant shield system to a circuit board (14) comprising a crystal oscillator (the radio-frequency bands component 12, para-0040+) such that the plurality of walls of the material contaminant shield system surround the crystal oscillator (12); and
coupling the material contaminant shield system (18) to the circuit board (14) to form a shielded oscillator system, and except for the coupled material contaminant shield system is configured to prevent an under-fill material applied at a location outside of the coupled material contaminant shield system from contaminating the crystal oscillator.
Muranaga teaches the circuit board component (5) coupled to the circuit board (1) via an underfill material (8), so that the material contaminant shield is configured to prevent the under-fill material from the circuit board component from contaminating the electronic device.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Muranaga employed in the electronic device of Foster in order to prevent solder slash and short circuit for the chip or component mounted on the circuit board.
Regarding claim 22, Foster as modified by Muranaga discloses providing the material contaminant shield system (18 or 20) comprises disposing the material contaminant shield system next to a circuit board component (12) such that a second wall of the plurality of walls is disposed between the circuit board component and the second wall.
Regarding claim 23, Foster as modified by Muranaga discloses the contaminant shield system is provided using a pick-and-place device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Muranaga, and further in view of DiPoala (U.S. 2005/0078468).
Regarding claim 4, Foster as modified by Muranaga discloses the material contaminant shield (18) comprises a first wall having a first thickness, wherein the first wall is disposed between the electronic device (12) and the circuit board component (12), and except for the material contaminant shield (18) comprises a second wall having a second thickness greater than the first thickness.
DiPoala teaches a shielding assembly (40) as shown in figures 1-5 comprising a
first wall (the length of the sidewall) having a first thickness, wherein the first wall is
disposed between the electronic device (the oscillator mounted in the chamber 46) and
the circuit board component (32a-32c), and wherein the contaminant shield (42)
comprises a second wall (the width of the sidewall) having a second thickness greater
than the first thickness (para-0005+, see figure 5).
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of DiPoala employed in the electronic device of
Foster and Muranaga in order to provide excellent mounting structure for the shielding assembly mounted on the circuit board.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Muranaga, and further in view Bogursky et al. (U.S. 2010/0157566) cited in the record.
Regarding claims 16-17, Foster as modified by Muranaga discloses all of the limitations of claimed invention except for a height of the first wall is less than 0.7 mm, or the thickness of the first wall is less than 0.3 mm.
Bogursky discloses a height of the first wall is less than 0.7 mm, para-0091+, or a thickness of the first wall is less than 0.3 mm, para-0086+.
It would have been obvious to one having ordinary skill in the art before the
effective filling date to have a teaching of Bogursky employed in the electronic device of
Foster and Muranaga in order to minimize size and high-density structure.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T DINH/Primary Examiner, Art Unit 2848