Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statements (IDS) were submitted on 8/16/23, 3/2/24, 5/10/24, and 6/9/25. Accordingly, the information disclosure statements are being considered by the examiner and initialed copies of the forms are attached to this correspondence.
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/22/25.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Patent Application Publication No. 2022/0165747) (“Yang”) in view of Lee (US Patent Application Publication No. 2019/0115356) (“Lee”).
Regarding Claim 1, Yang teaches a semiconductor structure, comprising: alternating stacks of insulating layers and electrically conductive layers located over a substrate (see Figure 3B, item 130), wherein each of the alternating stacks laterally extends along a first horizontal direction (see Figure 3B), wherein the alternating stacks are laterally spaced apart from each other along a second horizontal direction by backside trenches that laterally extend along the first horizontal direction (see Figure 3A, note trenches S1 and S2), and wherein the backside trenches comprise first backside trenches (S1) and second backside trenches (S2) that are interlaced along the second horizontal direction perpendicular to the first horizontal direction (see Figure 3A); first backside trench fill structures (Figure 11D, item 514) located in the first backside trenches, wherein each of the first backside trench fill structures comprises a respective first backside support bridge structure (Figure 11D, item 514) located at a first vertical spacing from the substrate (see height depicted in Figure 3A from substrate); and second backside trench fill structures (Figure 11D, item 504) located in the second backside trenches, wherein each of the second backside trench fill structures comprises a second backside support bridge structure (Figure 11D, item 504) located at a second vertical spacing from the substrate that is different from the first vertical spacing (see height depicted in Figure 3A from substrate), and wherein the second backside trenches do not include the first backside support trench fill structures located at the first vertical spacing from the substrate (see Figures 3A and 3B).
Yang does not specifically teach that the backside trench fill structures comprise respective sets of support bridge structures. However, Lee teaches forming fill structures in sets of segmented bridge structures (Figure 1, items SA) in a 3D memory structure. It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the segmented bridge structures of Lee in the device of Yang in order to obtain the known benefits of reduced structural distortion such as bended of stacked gate structures (¶0220).
Regarding Claim 2, Yang as modified by Lee further teaches the first backside trenches do not include the second backside support trench fill structures located at the second vertical spacing from the substrate (see Figure 3A of Yang).
Regarding Claim 3, Yang further teaches the first and the second backside support trench fill structures comprise a doped semiconductor material (¶0038).
Regarding Claim 4, Yang further teaches a vertical plane extending in the second horizontal direction passes through a plurality of the first and the second backside support trench fill structures (see Figures 3A and 3B)
Regarding Claim 5, Yang further teaches each of the first backside trench fill structures and the second backside trench fill structures further comprises a respective backside insulating spacer (Figure 11B, items 502+512) contacting sidewalls of a respective pair of alternating stacks of the alternating stacks; and each of the first backside trench fill structures and the second backside trench fill structures further comprises a respective backside contact (Figure 11B, items 504+514) via structure that is laterally surrounded by the respective backside insulating spacer
Regarding Claim 6, Yang further teaches a semiconductor material layer located above or within the substrate (Figure 11D, item 110); and source regions embedded within the semiconductor material layer and contacting a bottom surface of a respective one of the backside contact via structures (Figure 11D and ¶0023).
Regarding Claim 14, Yang further teaches first backside bridge support structures comprise depth variable support structures having respective bottom surfaces located at different vertical levels from the substrate (see Figure 3B, note bottom surface level differences in S1 and S2).
Allowable Subject Matter
Claims 7-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art, alone or in combination, teaches the language “each backside contact via structure within a respective first backside trench fill structure contacts top surfaces of each first backside support bridge structure within the respective first backside trench fill structure; and each backside contact via structure within a respective second backside trench fill structure is not in direct contact with any second backside support bridge structure within the respective second backside trench fill structure” of Claim 7, “each backside insulating spacer located within a respective first backside trench fill structure contacts bottom surfaces of each first backside support bridge structure within the respective first backside trench fill structure; and each backside insulating spacer located within a respective second backside trench fill structure contacts bottom surfaces of each second backside support bridge structure within the respective second backside trench fill structure” of Claim 8, and “each of the alternating stacks of insulating layers and electrically conductive layers comprises a respective insulating cap layer having a respective top surface within a first horizontal plane in which top surfaces of the second backside support bridge structures are located; and wherein each of the alternating stacks of insulating layers and electrically conductive layers comprise a respective additional insulating cap layer having a respective top surface within a second horizontal plane in which top surfaces of the first backside support bridge structures are located” of Claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al. (US Patent Application Publication No. 2017/0047334)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891