DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1, Fig. 6 and Fig. 8A in the reply filed on 01/13/2026 is acknowledged.
Accordingly, claims 6-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR10-2022-0132215 filed on 01/13/2026. The foreign application is not in English. The certified copy of the foreign priority application KR10-2022-0132215 has not been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application KR10-2022-0132215 that is not in English, an English translation of the non-English language foreign application KR10-2022-0132215 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Okano (US Pub. 20100231490).
Regarding claim 1, Okano discloses in Fig. 1-Fig. 3 a display panel comprising:
a base layer [1];
a circuit layer [11, 13, 33-35] on the base layer [1] and comprising a pixel circuit; and
a light emitting element layer on the circuit layer [11, 13, 33-35], wherein the light emitting element layer comprises:
a first electrode [3] on the circuit layer [11, 13, 33-35];
a light emitting pattern [4] on the first electrode [3];
a second electrode [5] on the light emitting pattern [3]; and
an upper pixel definition layer [6, 8, 21, 22 and portions of 5 formed on 6] on the circuit layer and having an upper opening [opening corresponding to the light emitting area] defined therein, the upper pixel definition layer [6, 8, 21, 22 and portions of 5 formed on 6] comprises a first part [portions of 5 formed on 6] electrically connected to the second electrode [5] and a second part [21 and 22] electrically insulated from the first part [portions of 5 formed on 6], and the second part [21 and 22] is surrounded by the first part [portions of 5 formed on 6] in a plan view.
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Regarding claim 2, Okano discloses in Fig. 1
wherein the circuit layer further comprises a connection metal [34] electrically connected to the second part.
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Regarding claims 3-4, Okano discloses in Fig. 1
wherein the light emitting element layer further comprises a lower pixel definition layer under the upper pixel definition layer and having a light emitting area defined therein;
wherein the circuit layer further comprises a first cap metal [35, 34, or 11] under the second part and overlapping at least a portion of the second part in a plan view.
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Claims 1, 3-5, 14, 17-18 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yoshizumi et al. (US Pub. 20170010712).
Regarding claim 1, Yoshizumi et al. discloses in Fig. 2A-Fig. 2B, Fig. 14B a display panel comprising:
a base layer [21];
a circuit layer on the base layer [21] and comprising a pixel circuit [70, 23, 24]; and
a light emitting element layer on the circuit layer, wherein the light emitting element layer comprises:
a first electrode [36] on the circuit layer;
a light emitting pattern [37] on the first electrode [36];
a second electrode [38] on the light emitting pattern [37]; and
an upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] on the circuit layer and having an upper opening [opening corresponding to the light emitting area] defined therein, the upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] comprises a first part [portions of 38 formed on 82] electrically connected to the second electrode [38] and a second part [27, 29, 28] electrically insulated from the first part [portions of 38 formed on 82], and the second part [27, 29, 28] is surrounded by the first part [portions of 38 formed on 82] in a plan view.
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Regarding claims 3-4, Yoshizumi et al. discloses in Fig. 2A-Fig. 2C
wherein the light emitting element layer further comprises a lower pixel definition layer [82] under the upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] and having a light emitting area defined therein;
wherein the circuit layer further comprises a first cap metal [24] under the second part and overlapping at least a portion of the second part in a plan view.
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Regarding claim 5, Yoshizumi et al. discloses in Fig. 2A-2C, Fig. 16C wherein the pixel circuit comprises:
a driving transistor [70]; and
a capacitor [85] connected between a gate electrode of the driving transistor [70] and a driving voltage line [55] to which a driving voltage is provided, and the second part [27, 28, 29] and the first cap metal [24] constitutes the capacitor.
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Regarding claim 14, Yoshizumi et al. discloses in Fig. 2A-2C, paragraph [0107]
wherein the upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] comprises a first conductive layer [27] and a second conductive layer [28] on the first conductive layer [27].
Regarding claim 17, Yoshizumi et al. discloses in Fig. 2A-Fig. 2C, Fig. 14B, Fig. 16C a display panel comprising:
a base layer [21];
a circuit layer on the base layer [21] and comprising a pixel circuit [70, 23, 24];
a light emitting element layer on the circuit layer; and
an encapsulation layer [61] on the light emitting element layer,
wherein the pixel circuit [70, 23, 24] comprises:
a driving transistor [70]; and
a capacitor [85] connected between a gate electrode of the driving transistor and a driving voltage line configured to receive a driving voltage [Fig. 16C],
the light emitting element layer comprises:
a first electrode [36] on the circuit layer and electrically connected to the pixel circuit [70];
a light emitting pattern [37] on the first electrode [36];
a second electrode [38] on the light emitting pattern [37]; and
an upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] on the circuit layer and having an upper opening [opening corresponding to the light emitting area] defined therein, the upper pixel definition layer [27, 29, 28 and portions of 38 formed on 82] comprises a first part [portions of 38 formed on 82] electrically connected to the second electrode [38] and a second part [27, 29, 28] constituting the capacitor.
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Regarding claim 18, Yoshizumi et al. discloses in Fig. 2A-Fig. 2C, Fig. 14B
wherein a slit is defined between the first part and the second part of the upper pixel definition layer, and a shape of the slit is a polygon or a ring in a plan view [ring shape, Fig. 14B].
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshizumi et al. (US Pub. 2017000712) as applied to claim 1 and claim 17 above and in view of Okano (US Pub. 20100231490).
Regarding claims 2 and 20, Yoshizumi et al. fails to disclose
wherein the circuit layer further comprises a connection metal electrically connected to the second part.
Okano discloses in Fig. 1
wherein the circuit layer further comprises a connection metal [34] electrically connected to the second part.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okano into the method of Yoshizumi et al. to include wherein the circuit layer further comprises a connection metal electrically connected to the second part. The ordinary artisan would have been motivated to modify Yoshizumi et al. in the above manner for the purpose of improving aperture ratio and reducing the parasitic capacitance [paragraph [0061] of Okano].
Claims 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshizumi et al. (US Pub. 2017000712) as applied to claim 1 and claim 17 above and in view of Kim et al. (US Pub. 20130248867).
Regarding claim 13, Yoshizumi et al. discloses in Fig. 2A-2C
an encapsulation layer [61] on the light emitting element layer, wherein the encapsulation layer [61] fills a space between the first part and the second part and covers the light emitting element layer.
Yoshizumi et al. fails to disclose
the encapsulation layer comprising an organic encapsulation layer.
Kim et al. discloses in Fig. 1, paragraph [0086]
the encapsulation layer [118] comprising an organic encapsulation layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Yoshizumi et al. to include the encapsulation layer comprising an organic encapsulation layer. The ordinary artisan would have been motivated to modify Yoshizumi et al. in the above manner for the purpose of providing suitable material of the encapsulation layer [paragraph [0086] of Kim et al.].
Regarding claim 19, Yoshizumi et al. discloses in Fig. 2A-2C
the slit is filled with the encapsulation layer [61].
Yoshizumi et al. fails to disclose
the encapsulation layer comprising an organic encapsulation layer.
Kim et al. discloses in Fig. 1, paragraph [0086]
the encapsulation layer [118] comprising an organic encapsulation layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Yoshizumi et al. to include the encapsulation layer comprising an organic encapsulation layer. The ordinary artisan would have been motivated to modify Yoshizumi et al. in the above manner for the purpose of providing suitable material of the encapsulation layer [paragraph [0086] of Kim et al.].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshizumi et al. (US Pub. 2017000712) as applied to claim 1 above and in view of Jeong et al. (US Pub. 20110108831)
Regarding claim 16, Yoshizumi et al. fails to disclose
a protection pattern configured to cover at least a portion of a top surface of the first electrode.
Jeong et al. discloses in Fig. 1, paragraph [0036]
a protection pattern [12] configured to cover at least a portion of a top surface of the first electrode [11].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Jeong et al. into the method of Yoshizumi et al. to include a protection pattern configured to cover at least a portion of a top surface of the first electrode. The ordinary artisan would have been motivated to modify Yoshizumi et al. in the above manner for the purpose of protecting the first electrode from subsequent etching step on the first electrode [paragraph [0036] of Jeong et al.].
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “wherein, in the first part, a side surface of the second conductive layer protrudes further toward a central direction of the light emitting area than a side surface of the first conductive layer” of claim 15 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893