DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-9 in the reply filed on 11/24/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIU et al [CN 114373764] IDS.
With respect to claim 1, LIU et al (figs. 1-7c) disclose a semiconductor structure comprising:
a substrate (100, fig. 4b);
an storage array (30, fig. 7a) located on the substrate and comprising a plurality of memory cells arranged in an array along a first direction (X) and a second direction (Y), each of the memory cells comprising a transistor structure, the transistor structure comprising a gate electrode (204, fig. 7a) and an active area (201, 202’, 203’), and the active area comprising a first active area and a second active area distributed on opposite sides of the gate electrode (204, fig. 7a) along the first direction, wherein the first direction and the second direction are both parallel to a top surface of the substrate and the first direction is perpendicular to the second direction;
a word line (403) extending along the second direction, being continuously and electrically connected with a plurality of gate electrodes in the memory cells arranged at intervals along the second direction; and
a bit line (402’) extending along the first direction, located on outside of each of the memory cells along the second direction, being continuous and electrically connected with the first active areas and the second active areas in a plurality of the memory cells arranged at intervals along the first direction.
With respect to claim 2, LIU et al (fig. 7c) disclose wherein the first active area (201, 202’, 203’) comprises a first channel region (210), and a first source region (203’) and a first drain region (202’) distributed on opposite sides of the first channel region along a third direction, and the third direction is perpendicular to the top surface of the substrate; and the second active area (201, 202’, 203’) comprises a second channel region (210), and a second source region (203’) and a second drain region (202’) distributed on opposite sides of the second channel region along the third direction, and the first channel region and the second channel region are symmetrically distributed with respect to the gate electrode (204).
With respect to claim 3, LIU et al (fig. 7c) disclose wherein the semiconductor structure further comprises: a bit line contact (401’) array located below the storage array, comprising a plurality of bit line contact structures arranged in an array along the first direction and the second direction; wherein the bit line contact structures are electrically connected with the active area in the transistor structure, and a plurality of the bit line contact structures arranged at intervals along the first direction are electrically connected with a same one bit line.
With respect to claim 4, LIU et al (fig. 7b) disclose wherein the bit line contact (401) array and the memory array (302) are arranged in a staggered way; and each of the bit line contact structures is in contact and electrical connection with two active areas adjacent along the first direction, and each of the active areas is in contact and electrical connection with two bit line contact structures adjacent along the first direction.
With respect to claim 5, LIU et al (fig. 7b-7c) disclose wherein for one bit line contact structure (401’) located between two adjacent ones of the memory cells along the first direction, one end of the one bit line contact structure along the first direction is electrically connected with the first source region (203’) in one of the two adjacent memory cells, and another end of the one bit line contact structure along the first direction is electrically connected with the second source region (203’) in another of the two adjacent memory cells; and the two bit line contact structures in contact and electrical connection with the active area are symmetrically distributed with respect to an axis of the active area, and the axis extends along the second direction.
With respect to claim 6, LIU et al (fig. 7a-7c) disclose wherein a projection of the bit line contact structure (401) on the top surface of the substrate has a same shape and a same size as a shape and size of a projection of the active area on the top surface of the substrate; and a distance between two adjacent bit line contact structures is equal to a distance between two adjacent active areas.
With respect to claim 7, LIU et al (fig. 7a-7c) disclose wherein each of the memory cells further comprises: a capacitor structure (302, 302’) located above the transistor structure, being electrically connected with the first drain region and the second drain region, wherein a projection of the capacitor structure on the top surface of the substrate at least completely covers a projection of the active area on the top surface of the substrate.
With respect to claim 8, LIU et al (fig. 7a-7c) disclose wherein the each of the memory cells further comprises: a node contact structure (301, 301’) located between the capacitor structure and a transistor, wherein one end of the node contact structure is in contact and electrical connection with the first drain region and the second drain region, and another end of the node contact structure is in contact and electrical connection with the capacitor structure.
With respect to claim 9, LIU et al (fig. 1g) disclose wherein a plurality of word lines (WL) are arranged at intervals along the first direction and a plurality of bit lines (BL) are arranged at intervals along the second direction; and a distance between two adjacent word line along the first direction, a distance between two adjacent bit lines along the second direction, and a distance between two adjacent ones of the memory cells are all equal to each other.
Conclusion
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/HOAI V PHAM/Primary Examiner, Art Unit 2892