Prosecution Insights
Last updated: April 19, 2026
Application No. 18/451,060

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SEMICONDUCTOR PACKAGE STRUCTURE

Non-Final OA §103§112
Filed
Aug 16, 2023
Examiner
KARIMY, TIMOR
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Changxin Memory Technologies Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
827 granted / 1011 resolved
+13.8% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
48 currently pending
Career history
1059
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
22.8%
-17.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1011 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12 in the reply filed on 01/15/2026 is acknowledged. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Claim 3: “wherein the adhesive film comprises a first adhesive film, and a second adhesive film located on the first adhesive film” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “a plurality of second conductive bumps” in lines 6-7. The limitation raises ambiguity as it implies that there is a plurality of first conductive bumps that is not recited in the claim. Correction/clarification is required. Claims 2-12 are rejected for being dependent on claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US Pub. 2010/0301475) in view of LEE et al. (US Pub. 2015/0041971). Regarding claim 1, Hsu teaches a semiconductor package structure, comprising: a first substrate 400 (Fig. 10); a first semiconductor die 360 connected to the first substrate 400 (Fig. 10); and a second semiconductor die stack structure 500 located on the first semiconductor die 360, the second semiconductor die stack structure 500 including a plurality of second semiconductor dies sequentially stacked onto one another in a first direction (see Fig. 10 and Para [0029]) Hsu is silent on a plurality of second conductive bumps being formed on a side of the second semiconductor die stack structure in the first direction, wherein the first direction is a direction parallel to a plane where the first substrate is located; and a second substrate, a signal line in the second substrate being connected to the plurality of second conductive bumps, and the second substrate being connected to the first substrate in a direction perpendicular to the plane where the first substrate is located. However, LEE teaches a plurality of second conductive bumps 170 being formed on a side of the second semiconductor die stack structure 1 in the first direction, wherein the first direction is a direction parallel to a plane where a first substrate 110 is located; and a second substrate 150, a signal line 151 in the second substrate 150 being connected to the plurality of second conductive bumps 170, and the second substrate 150 being connected to the first substrate110 in a direction perpendicular to the plane where the first substrate is located (see Fig. 2). This has the advantages of providing high density chip integration, improved signal integrity and reduced power consumption. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hsu with the conductive bumps and the second substrate, as taught by LEE, so as to obtain an improved semiconductor device. Regarding claim 2, the combination of Hsu and LEE teaches the semiconductor package structure according to claim 1, wherein the first semiconductor die 360 comprises a logic die, and the second semiconductor die stack structure comprises DRAM dies (Hsu’s Fig. 10). Regarding claim 5, the combination of Hsu and LEE teaches the semiconductor package structure according to claim 1, wherein the first semiconductor die 360 and the second semiconductor die stack structure 500 communicate with each other in a wireless manner (Fig. 10 & Fig. 2). Regarding claim 8, the combination of Hsu and LEE teaches the semiconductor package structure according to claim 1, further comprising: a plurality of through silicon vias 96, each of the plurality of through silicon vias 96 penetrating through a respective one of the plurality of second semiconductor dies in the first direction (Hsu’s Fig. 10); and a plurality of fourth conductive bumps (note the bumps between each semiconductor dies in the die stack 500, Fig. 10) located between any two adjacent second semiconductor dies of the plurality of second semiconductor dies, each of the plurality of fourth conductive bumps being connected to a respective one of the plurality of through silicon vias 96, wherein each of the plurality of second conductive bumps is connected to a respective one of the plurality of through silicon vias and a respective one of the plurality of fourth conductive bumps (Hsu’s Fig. 10). Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over 103 as applied to claim 1 above, and further in view of Lee (US Pub. 2021/0074660). Regarding claim 3, the combination of Hsu and LEE is on the semiconductor package structure according to claim 1, further comprising: an adhesive film located between the first semiconductor die and the second semiconductor die stack structure. However, Lee teaches in Fig. 2 an adhesive film (580 and/or 270) located between a first semiconductor die 100 and a second semiconductor die stack structure (see die stack 200-400). This has the advantages of providing adhesion and protection. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hsu & LEE with the adhesive/protective film, as taught by Lee, so as to obtain an improved semiconductor device. Regarding claim 4, the combination of Hsu and LEE the semiconductor package structure according to claim 3, wherein the adhesive film comprises a first adhesive film 280, and a second adhesive film 270 located on the first adhesive film, wherein an elastic modulus of the second adhesive film 270 is greater than an elastic modulus of the first adhesive film 280 (Fig. 1 and associated text). Allowable Subject Matter Claims 6-7 & 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOR KARIMY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 16, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604472
SEMICONDUCTOR DEVICE INCLUDING STACK STRUCTURE AND TRENCHES
2y 5m to grant Granted Apr 14, 2026
Patent 12604784
STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12598872
DISPLAY PANEL, METHOD OF MANUFACTURING THE SAME, AND SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
Patent 12588460
SENSOR CONFIGURATION FOR PROCESS CONDITION MEASURING DEVICES
2y 5m to grant Granted Mar 24, 2026
Patent 12588278
SEMICONDUCTOR DEVICE HAVING DIFFERENT SIZE ACTIVE REGIONS AND METHOD OF MAKING
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+10.2%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1011 resolved cases by this examiner. Grant probability derived from career allow rate.

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