DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-6 & 8-13 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(3) as being anticipated by TONG et al. (US Pub. 2024/0047298).
Regarding claim 1, TONG teaches a semiconductor structure, comprising:
a carrier structure (see Fig. 43 below); and
a stack structure located on the carrier structure, wherein the stack structure comprises at least one heat dissipation panel and at least one die module stacked onto one another (see Fig. 43 below and note the annotations), and the at least one die module comprises a plurality of dies stacked onto one another at least one die, the plurality of dies are stacked by hybrid bonding (TONG teaches in Para [0282 & 0292], wherein the plurality of dies are stacked by hybrid-bonding, Fig. 43),
wherein an area of an orthographic projection of the at least one heat dissipation panel on the carrier structure is greater than an area of an orthographic projection of the at least one die module on the carrier structure (see Fig. 43 below and note the area of orthographic projection of the at least one heat dissipation panel), each of the plurality of dies comprises a front surface and a back surface opposite to each other, and the front surface of at least one of the plurality of dies is disposed to face the at least one heat dissipation panel (see Fig. 43 below and note the active font surface of the bottommost die within the module facing the heat dissipation panel).
PNG
media_image1.png
776
1044
media_image1.png
Greyscale
Regarding claim 5, TONG teaches the semiconductor structure according to claim 1, further comprising: a package structure (e.g. 100N6, 100N2 & 100N7) covering a part of a surface of the at least one heat dissipation panel and exposing at least an outer peripheral surface of the at least one heat dissipation panel, wherein the package structure also covers the at least one die module (Fig. 43).
Regarding claim 6, TONG teaches the semiconductor structure according to claim 1, wherein a plurality of welding parts are arranged between the at least one die module and the at least one heat dissipation panel (e.g. chip pads between dies and the heat dissipation panel in Fig. 43).
Regarding claim 8, TONG teaches the semiconductor structure according to claim 6, wherein at least one of the plurality of welding parts is located at an edge of the at least one die module (Fig. 43).
Regarding claim 9, TONG teaches the semiconductor structure according to claim 6, wherein the plurality of welding parts are symmetrically distributed relative to a center of the at least one die module (Fig. 43).
Regarding claim 10, TONG teaches the semiconductor structure according to claim 1, wherein the orthographic projection of the at least one die module on the carrier structure is located at a center position of the orthographic projection of the at least one heat dissipation panel on the carrier structure (see Fig. 43 above).
Regarding claim 11, TONG teaches the semiconductor structure according to claim 1, wherein a thickness of the at least one heat dissipation panel is less than a thickness of the at least one die in a direction perpendicular to an upper surface of the carrier structure (see Fig. 43 above).
Regarding claim 12, TONG teaches the semiconductor structure according to claim 1, wherein the stack structure comprises a plurality of heat dissipation panels, and orthographic projections of the plurality of heat dissipation panels on the carrier structure have a same area (note components 100N61 & 100N2 that further comprises the heat dissipation panel in Fig. 43).
Regarding claim 13, TONG teaches the semiconductor structure according to claim 1, wherein the stack structure comprises a plurality of die modules, and a thickness of the at least one heat dissipation panel is proportional to a number of dies in a die module, closest to the at least one heat dissipation panel, of the plurality of die modules (see Fig. 43 above).
Allowable Subject Matter
Claims 2-4, 7 & 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 5-6 & 8-13 have been considered but are moot in light of new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818