DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-14 & 17-18 in the reply filed on March 19, 2014 is acknowledged. The traversal is on the grounds that the species identified in the restriction requirement are not distinct. This is not agreed upon as the species are structurally different from one another that require searching different classes/subclasses, electronic resources, and/or employing different search queries. Furthermore, the Examiner withdraws claim 14 from examination as it is directed towards non-elected Species D (Fig. 4). As such, claims 1-13 & 17-18 have been considered for examination.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-6 & 8-13 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Ngai et al. (US Patent 8,941,233).
Regarding claim 1, Ngai teaches a semiconductor structure, comprising:
a carrier structure 108 (Fig. 1B); and
a stack structure located on the carrier structure 108 (see Fig. 1B below), wherein the stack structure comprises at least one heat dissipation panel 125 and at least one die module (102A, 102B or 102C) stacked onto one another, and the at least one die module comprises at least one die (e.g. 102A or 102B, Fig. 1B),
wherein an area of an orthographic projection of the at least one heat dissipation panel 125 on the carrier structure 108 is greater than an area of an orthographic projection of the at least one die module on the carrier structure 108 (Fig. 1B).
PNG
media_image1.png
680
948
media_image1.png
Greyscale
Regarding claim 2, Ngai teaches the semiconductor structure according to claim 1, wherein the stack structure comprises a plurality of die modules (102A-102D) and a plurality of heat dissipation panels 125, and each of the plurality of die modules alternates with a respective one of the plurality of heat dissipation panels in a direction perpendicular to an upper surface of the stack structure (see Fig. 1B).
Regarding claim 5, Ngai teaches the semiconductor structure according to claim 1, further comprising: a package structure covering a part of a surface of the at least one heat dissipation panel and exposing at least an outer peripheral surface of the at least one heat dissipation panel, wherein the package structure also covers the at least one die module (note that an outer peripheral surface of the at least one heat dissipation panel is exposed prior to deposition of the package encapsulant, Fig. 1B).
Regarding claim 6, Ngai teaches the semiconductor structure according to claim 1, wherein a plurality of welding parts (e.g. chip pads or pads 107 between dies and heat dissipation panel in Fig. 1B-2) are arranged between the at least one die module and the at least one heat dissipation panel .
Regarding claim 8, Ngai teaches the semiconductor structure according to claim 6, wherein at least one of the plurality of welding parts is located at an edge of the at least one die module (e.g. pads 107 towards the edges, see Fig. 1B).
Regarding claim 9, Ngai teaches the semiconductor structure according to claim 6, wherein the plurality of welding parts 107 are symmetrically distributed relative to a center of the at least one die module (Fig. 1B-2).
Regarding claim 10, Ngai teaches the semiconductor structure according to claim 1, wherein the orthographic projection of the at least one die module (e.g. 102A or 102B) on the carrier structure is located at a center position of the orthographic projection of the at least one heat dissipation panel 125 on the carrier structure 108 (Fig. 1B).
Regarding claim 11, Ngai teaches the semiconductor structure according to claim 1, wherein a thickness of the at least one heat dissipation panel 125 is less than a thickness of the at least one die 102 in a direction perpendicular to an upper surface of the carrier structure (Fig. 1B).
Regarding claim 12, Ngai teaches the semiconductor structure according to claim 1, wherein the stack structure comprises a plurality of heat dissipation panels 125, and orthographic projections of the plurality of heat dissipation panels on the carrier structure have a same area (see Fig. 1B).
Regarding claim 13, Ngai teaches the semiconductor structure according to claim 1, wherein the stack structure comprises a plurality of die modules (102A-102D), and a thickness of the at least one heat dissipation panel 125 is proportional to a number of dies in a die module, closest to the at least one heat dissipation panel, of the plurality of die modules (see Fig. 1B, also see top view shown in Fig. 1C, 3B & 4B, wherein thickness of heat dissipation panel is proportional to the die/s).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ngai as applied to claim 1 above, and in further view of Huang (US Patent 6,559,525).
Regarding claim 2, while Ngai teaches the semiconductor structure according to claim 1, wherein the at least one die (e.g. 102A or 102B) comprises a front surface and a back surface opposite to each other, the stack structure comprises a plurality of heat dissipation panels 125; however, Ngai is silent on the at least one die module comprises a plurality of dies stacked onto one another, the plurality of dies comprise a die located at a top layer of the at least one die module and another die located at a bottom layer of the at least one die module, and each of a front surface of the die located at the top layer of the at least one die module and a front surface of the another die located at the bottom layer of the at least one die module faces a respective one of the plurality of heat dissipation panels. However, Huang teaches in Fig. 7, wherein at least one die module (330 & 340) comprises a plurality of dies stacked onto one another, the plurality of dies comprise a die 330 located at a top layer of the at least one die module and another die 340 located at a bottom layer of the at least one die module, and each of a front surface of the die 330 located at the top layer of the at least one die module and a front surface of the another die 340 located at the bottom layer of the at least one die module faces a respective one of the plurality of heat dissipation panels (e.g. 310 & 360). This has the advantage of incorporating more dies to improve further miniaturization and increase device capability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Ngai with the die module, as taught by Huang, so as to improve scaling and miniaturization.
Regarding claim 4, the combination of Ngai and Huang teaches the semiconductor structure according to claim 3, wherein the at least one die module comprises two dies (330 & 340), and the front surface of each of the two dies faces a respective one of the plurality of heat dissipation panels (310 & 360, see Huang’s Fig. 7).
Allowable Subject Matter
Claims 7 & 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818