DETAILED ACTION
This action is responsive to the following communications: the Request for Continued Examination (with claim amendment) filed on April 8, 2026.
Claims 1-2, 4-5 and 16-17 are pending. Claims 3 and 18 are canceled. Claims 1 and 16-17 are amended. Claims 6-15 and 19-25 are withdrawn due to an Election/Restriction Requirement. Claims 1 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 8, 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190035797), in view of Shen et al. (US 20120307559).
Regarding independent claim 1, Lee discloses a semiconductor memory device [Fig. 9: 1120, para. 146] comprising:
a first cell string [Fig. 1A: SR11] coupled to a first bit line [Fig. 1A: BL1], the first cell string including a first drain select transistor [Fig. 1A: DSTa], a plurality of memory cells [Fig. 1A: MC1-MCn], and a first source select transistor [Fig. 1A: SSTa, para. 20-27]; and
a second cell string [Fig. 1A: SR21] coupled to the first bit line [Fig. 1A: BL1], the second cell string including a second drain select transistor, a plurality of memory cells, and a second source select transistor [see Fig. 1A, para. 20-27],
wherein a plurality of data bits are stored in a memory cell group formed by a first memory cell coupled to a first word line among the plurality of memory cells included in the first cell string, and a second memory cell coupled to the first word line among the plurality of memory cells included in the second cell string [see Fig. 1A, a group of memory cells of cell strings SR11 and SR21 is connected to a word line WL1 and stores data, para. 24 and 56],
wherein the second memory cell is a memory cell adjacent to the first memory cell among memory cells coupled to the first word line [see Fig. 1A, the memory cell MC1 of memory string SR11 is adjacent to the memory cell of memory string SR21 coupled to the word line WL1, para. 21 and 24], and
wherein the first source select transistor and the second source select transistor are controlled through an identical source select line shared by the first memory cell and the second memory cell adjacent the first memory cell [see Fig. 1A, each of the first memory strings SR11 to SR14 and the second memory strings SR21 to SR24 may include a source select transistor SSTa, SSTb or SSTc, a plurality of memory cell transistors MC1 to MCn (n is a natural number of 2 or more), and a drain select transistor DSTa, DSTb or DSTc, which are connected in series by a channel pillar, para. 23. Source select transistors SSTa of the memory strings SR11 and SR21 are controlled through an identical source select line SSLa, para. 25].
However, Lee is silent with respect to wherein a number of data bits stored in each of the first and second memory cells adjacent to each other is a non-integer and wherein a total number of data bits stored in the memory cell group is an integer number represented through a combination of threshold voltage states of the first memory cell and the second memory cell.
Shen et al. teach wherein a number of data bits stored in each of the first and second memory cells adjacent to each other is a non-integer [see Fig. 1, memory cell 111-1 of NAND string 109-1 is adjacent to memory cell 112-1 of NAND string 109-2, para. 14. Data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), para. 21], and wherein a total number of data bits stored in the memory cell group is an integer number represented through a combination of threshold voltage states of the first memory cell and the second memory cell [a memory cell can be programmed to one of a number of threshold voltage levels corresponding to either an integer or fractional number of bits. For example, in the embodiment illustrated in FIG. 1, data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), which are coupled to sense lines 107-1 and 107-2, could be combined by logic in control circuitry to output an integer number of bits, para. 22. Cells storing a fractional number of bits can be read as a group in combination with, at least, a number of cells corresponding to the inverse of a fractional remainder of the number of bits stored. For example, two 2
1
2
bit cells could be read together to produce a 5-bit output, and four 3
1
4
bit cells could be read together to produce a 13-bit output, para. 26].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee to the teaching of Shen et al. such that each of memory cells that is connected to the same word line in two adjacent cell strings as taught by Lee stores a non-integer number of data bits as taught by Shen et al. and through a combination of threshold voltage states of Lee’s first memory cell and second memory cell, a total number of data bits stored in the memory cell group is an integer number as taught by Shen et al. to increase storage density and reduce bit error rate [see Shen et al.’s para. 4 and 39].
Regarding claim 2, Lee in combination with Shen et al. teach the limitation with respect to claim 1.
Furthermore, Lee discloses the first cell string and the second cell string are disposed adjacent to each other [see Fig. 1A: SR11 and SR21, para. 20], and
the first drain select transistor and the second drain select transistor are controlled through different drain select lines [see Fig 1A, para. 26].
Regarding claim 4, Lee in combination with Shen et al. teach the limitation with respect to claim 1.
Furthermore, Shen et al. discloses wherein the first memory cell and the second memory cell are each programmed to one of an identical number of threshold voltage states [para. 28-31].
Regarding claim 5, Lee in combination with Shen et al. teach the limitation with respect to claim 4.
Furthermore, Shen et al. discloses wherein:
the first memory cell and the second memory cell are each programmed to one of three threshold voltage states [Fig. 4A, para. 47], and
the memory cell group stores three bits of data [Fig. 4A, para. 47].
Regarding independent claim 16, Lee discloses a semiconductor memory device [Fig. 9: 1120, para. 146] including a plurality of cell strings [Fig. 1A: SR11-SR21] coupled between a bit line [Fig. 1A: BL1] and a source line [Fig. 1: SA, para. 20], the plurality of cell strings each [Fig. 1A: SR11] comprising:
a drain select transistor [Fig. 1A: DSTa] coupled to the bit line [Fig. 1A: BL1, para. 23];
a source select transistor [Fig. 1A: SSTa] coupled to the source line [Fig. 1: SA, para. 23]; and
a plurality of memory cells [Fig. 1A: MC1-MCn] coupled in series between the drain select transistor and the source select transistor, and coupled to respective word lines [Fig. 1A: WL1-WLn, para. 24],
wherein a plurality of data bits are stored in a memory cell group formed by at least a part of the memory cells of the cell strings, the part being coupled to a first word line among the word lines [see Fig. 1A, a group of memory cells of cell strings SR11 and SR21 is connected to a word line WL1 and stores data, para. 24 and 56],
wherein a first source select transistor included in a first cell string and a second source select transistor included in a second cell string are controlled through an identical source select line [see Fig. 1A, source select transistors of the cell strings SR11 and SR21 are controlled through an identical source select line SSLa, para. 29].
wherein the memory cell group includes a first memory cell and a second memory cell [see Fig. 1A, a group of memory cells of cell strings SR11 and SR21 is connected to a word line WL1, para. 23-24],
wherein the second memory cell is a memory cell adjacent to the first memory cell among memory cells coupled to the first word line [see Fig. 1A, the memory cell MC1 of memory string SR11 is adjacent to the memory cell of memory string SR21 coupled to the word line WL1, para. 21 and 24], and
wherein the identical source select line is shared by the first memory cell and the second memory cell adjacent the first memory cell [see Fig. 1A, each of the first memory strings SR11 to SR14 and the second memory strings SR21 to SR24 may include a source select transistor SSTa, SSTb or SSTc, a plurality of memory cell transistors MC1 to MCn (n is a natural number of 2 or more), and a drain select transistor DSTa, DSTb or DSTc, which are connected in series by a channel pillar, para. 23. Source select transistors SSTa of the memory strings SR11 and SR21 are controlled through an identical source select line SSLa, para. 25].
However, Lee is silent with respect to wherein a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of memory cells of the part and a number of the data bits stored in each of the first and second memory cells adjacent to each other is a non-integer.
Shen et al. teach wherein a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of memory cells of the part [a memory cell can be programmed to one of a number of threshold voltage levels corresponding to either an integer or fractional number of bits. For example, in the embodiment illustrated in FIG. 1, data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), which are coupled to sense lines 107-1 and 107-2, could be combined by logic in control circuitry to output an integer number of bits, para. 22. Cells storing a fractional number of bits can be read as a group in combination with, at least, a number of cells corresponding to the inverse of a fractional remainder of the number of bits stored. For example, two 2
1
2
bit cells could be read together to produce a 5 bit output, and four 3
1
4
bit cells could be read together to produce a 13 bit output, para. 26] and a number of the data bits stored in each of the first and second memory cells adjacent to each other is a non-integer [see Fig. 1, memory cell 111-1 of NAND string 109-1 is adjacent to memory cell 112-1 of NAND string 109-2, para. 14. Data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), para. 21].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee to the teaching of Shen et al. such that a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of Lee’s memory cells of the part as taught by Shen et al. to increase storage density and reduce bit error rate [see Shen et al.’s para. 4 and 39].
Regarding claim 17, Lee in combination with Shen et al. teach the limitation with respect to claim 16.
Furthermore, Lee discloses wherein:
a first cell string [Fig. 1A: SR11] including the first memory cell and a second cell string [Fig. 1A: SR21] including the second memory cell are disposed adjacent to each other [see Fig. 1A, para. 20], and
a first drain select transistor included in the first cell string and a second drain select transistor included in the second cell string are controlled through different drain select lines [see Fig 1A, para. 26].
Response to Arguments
Applicant's arguments filed with respect to independent claims 1 and 16 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that neither Lee nor Shen discloses how memory cells storing non-integer bits and representing a total number of data bits are grouped in an interrelated manner. In particular, neither reference provides any teaching or suggestion regarding the physical relationship among the grouped memory cells. Further, the memory cell group in the claimed inventions is composed of memory cells connected to the same source select line. That is, as in claim 1, the "identical source select line shared by the first memory cell and the second memory cell adjacent the first memory cell." This configuration enables a read operation to be simultaneously performed on the memory cells storing the respective bits, thereby improving read speed. Again, neither Lee nor Shen provides any teaching or motivation toward such an arrangement, see Applicant’s Remarks pages 13-16. This particular remark is not considered persuasive.
Lee discloses in Figure 1A, first memory strings SR11 included in the first half group HG1 and second memory strings SR21 included in the second half group HG2 are connected to the bit lines BL1, wherein the memory cell MC1 of SR11 is adjacent to the memory cell of SR21 coupled to the word line WL1 [para. 21 and 24]. Moreover, SR11 and SR21 share the source select line SSLa [para. 27]. Therefore, the physical relationship among the grouped memory cells in Figure 1A of Lee reference is similar to the group of cell strings in Figure 7 of the application. Furthermore, Shen et al. teach in Figure 1, memory cell 111-1 of NAND string 109-1 is adjacent to memory cell 112-1 of NAND string 109-2 [para. 14] and data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits) [para. 21], see the augmented rejection above.
For the above reasons, the applied rejection is considered proper and maintained.
The other claims were argued for substantially the same reason, and the arguments are not persuasive for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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