DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on October 30, 2025 and the Foreign Priority papers retrieved on March 15, 2023.
Claims 1-2, 4-5 and 16-17 are pending. Claims 3 and 18 are canceled. Claims 1, 16-17, 19-21 and 24 are amended. Claims 6-15 and 19-25 are withdrawn due to an Election/Restriction Requirement. Claims 1 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings were received on October 30, 2025. These drawings are approved.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190035797), in view of Shen et al. (US 20120307559).
Regarding independent claim 1, Lee discloses a semiconductor memory device [Fig. 9: 1120, para. 146] comprising:
a first cell string [Fig. 1A: SR11] coupled to a first bit line [Fig. 1A: BL1], the first cell string including a first drain select transistor [Fig. 1A: DSTa], a plurality of memory cells [Fig. 1A: MC1-MCn], and a first source select transistor [Fig. 1A: SSTa, para. 20-27]; and
a second cell string [Fig. 1A: SR21] coupled to the first bit line [Fig. 1A: BL1], the second cell string including a second drain select transistor, a plurality of memory cells, and a second source select transistor [see Fig. 1A, para. 20-27],
wherein a plurality of data bits are stored in a memory cell group formed by a first memory cell coupled to a first word line among the plurality of memory cells included in the first cell string, and a second memory cell coupled to the first word line among the plurality of memory cells included in the second cell string [see Fig. 1A, a group of memory cells of cell strings SR11 and SR21 is connected to a word line WL1 and stores data, para. 24 and 56], and
wherein the first source select transistor and the second source select transistor are controlled through an identical source select line [see Fig. 1A, source select transistors of the cell strings SR11 and SR21 are controlled through an identical source select line SSLa, para. 29].
However, Lee is silent with respect to wherein a number of data bits stored in each of the first and second memory cells is a non-integer and wherein a total number of data bits stored in the memory cell group is an integer number represented through a combination of threshold voltage states of the first memory cell and the second memory cell.
Shen et al. teach wherein a number of data bits stored in each of the first and second memory cells is a non-integer [para. 24], and wherein a total number of data bits stored in the memory cell group is an integer number represented through a combination of threshold voltage states of the first memory cell and the second memory cell [a memory cell can be programmed to one of a number of threshold voltage levels corresponding to either an integer or fractional number of bits. For example, in the embodiment illustrated in FIG. 1, data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), which are coupled to sense lines 107-1 and 107-2, could be combined by logic in control circuitry to output an integer number of bits, para. 22. Cells storing a fractional number of bits can be read as a group in combination with, at least, a number of cells corresponding to the inverse of a fractional remainder of the number of bits stored. For example, two 2
1
2
bit cells could be read together to produce a 5 bit output, and four 3
1
4
bit cells could be read together to produce a 13 bit output, para. 26].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee to the teaching of Shen et al. such that each of memory cells that is connected to the same word line in two adjacent cell strings as taught by Lee stores a non-integer number of data bits as taught by Shen et al. and through a combination of threshold voltage states of Lee’s first memory cell and second memory cell, a total number of data bits stored in the memory cell group is an integer number as taught by Shen et al. to increase storage density and reduce bit error rate [see Shen et al.’s para. 4 and 39].
Regarding claim 2, Lee in combination with Shen et al. teach the limitation with respect to claim 1.
Furthermore, Lee discloses the first cell string and the second cell string are disposed adjacent to each other [see Fig. 1A: SR11 and SR21, para. 20], and
the first drain select transistor and the second drain select transistor are controlled through different drain select lines [see Fig 1A, para. 26].
Regarding claim 4, Lee in combination with Shen et al. teach the limitation with respect to claim 1.
Furthermore, Shen et al. discloses wherein the first memory cell and the second memory cell are each programmed to one of an identical number of threshold voltage states [para. 28-31].
Regarding claim 5, Lee in combination with Shen et al. teach the limitation with respect to claim 4.
Furthermore, Shen et al. discloses wherein:
the first memory cell and the second memory cell are each programmed to one of three threshold voltage states [Fig. 4A, para. 47], and
the memory cell group stores three bits of data [Fig. 4A, para. 47].
Regarding independent claim 16, Lee discloses a semiconductor memory device [Fig. 9: 1120, para. 146] including a plurality of cell strings [Fig. 1A: SR11-SR21] coupled between a bit line [Fig. 1A: BL1] and a source line [Fig. 1: SA, para. 20], the plurality of cell strings each [Fig. 1A: SR11] comprising:
a drain select transistor [Fig. 1A: DSTa] coupled to the bit line [Fig. 1A: BL1, para. 23];
a source select transistor [Fig. 1A: SSTa] coupled to the source line [Fig. 1: SA, para. 23]; and
a plurality of memory cells [Fig. 1A: MC1-MCn] coupled in series between the drain select transistor and the source select transistor, and coupled to respective word lines [Fig. 1A: WL1-WLn, para. 24],
wherein a plurality of data bits are stored in a memory cell group formed by at least a part of the memory cells of the cell strings, the part being coupled to a first word line among the word lines [see Fig. 1A, a group of memory cells of cell strings SR11 and SR21 is connected to a word line WL1 and stores data, para. 24 and 56],
wherein a first source select transistor included in a first cell string and a second source select transistor included in a second cell string are controlled through an identical source select line [see Fig. 1A, source select transistors of the cell strings SR11 and SR21 are controlled through an identical source select line SSLa, para. 29].
However, Lee is silent with respect to wherein a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of memory cells of the part.
Shen et al. teach wherein a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of memory cells of the part [a memory cell can be programmed to one of a number of threshold voltage levels corresponding to either an integer or fractional number of bits. For example, in the embodiment illustrated in FIG. 1, data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), which are coupled to sense lines 107-1 and 107-2, could be combined by logic in control circuitry to output an integer number of bits, para. 22. Cells storing a fractional number of bits can be read as a group in combination with, at least, a number of cells corresponding to the inverse of a fractional remainder of the number of bits stored. For example, two 2
1
2
bit cells could be read together to produce a 5 bit output, and four 3
1
4
bit cells could be read together to produce a 13 bit output, para. 26].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lee to the teaching of Shen et al. such that a total number of data bits stored in the memory cell group is represented through a combination of threshold voltage states of Lee’s memory cells of the part as taught by Shen et al. to increase storage density and reduce bit error rate [see Shen et al.’s para. 4 and 39].
Regarding claim 17, Lee in combination with Shen et al. teach the limitation with respect to claim 16.
Furthermore, Lee discloses wherein:
the memory cell group includes first and second memory cells among the memory cells of the cell strings [see Fig. 1A, two memory cells of the cell strings SR11 and SR21],
a first cell string [Fig. 1A: SR11] including the first memory cell and a second cell string [Fig. 1A: SR21] including the second memory cell are disposed adjacent to each other [see Fig. 1A, para. 20], and
a first drain select transistor included in the first cell string and a second drain select transistor included in the second cell string are controlled through different drain select lines [see Fig 1A, para. 26].
Response to Arguments
Applicant's arguments filed with respect to independent claims 1 and 16 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that the Lee reference neither discloses a memory cell group corresponding to the present application nor teaches that the memory cells of such a memory cell group are controlled through an identical source select line. Furthermore, Shen appears to disclose reading memory cells that store non-integer data bits to confirm data, however, Shen does not disclose controlling such memory cells storing non- integer data bits through the same source select line. Accordingly, even when combining the disclosures of Shen and Lee, the features of Applicant's claim 1 cannot be readily derived, see Applicant’s Remarks page 16. This particular remark is not considered persuasive.
Lee discloses source select transistors of the cell strings SR11 and SR21 are controlled through an identical source select line SSLa [para. 29]. Furthermore, Shen et al. describe a memory cell can be programmed to one of a number of threshold voltage levels corresponding to either an integer or fractional number of bits. For example, in the embodiment illustrated in FIG. 1, data from cells 111-1 and 112-1, each storing a number of bits with a 1/2 fractional remainder, (e.g., 21/2 bits), which are coupled to sense lines 107-1 and 107-2, could be combined by logic in control circuitry to output an integer number of bits [para. 22], see the augmented rejection above.
For the above reasons, the applied rejection is considered proper and maintained.
The other claims were argued for substantially the same reason, and the arguments are not persuasive for the same reason.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825