Prosecution Insights
Last updated: October 01, 2026
Application No. 18/451,104

SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION

Final Rejection §112
Filed
Aug 17, 2023
Priority
Mar 15, 2023 — RE 10-2023-0033794
Examiner
LUONG, DUY HAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
4 (Final)
95%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
39 granted / 41 resolved
+27.1% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
73
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
59.1%
+19.1% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 41 resolved cases

Office Action

§112
DETAILED ACTION This action is responsive to the following communications: the Amendment filed on August 27, 2026. Claims 1-2, 4-5 and 16-17 are pending. Claims 3 and 18 are canceled. Claims 1 and 16 are amended. Claims 1 and 16 are independent. Claims 6-15 and 19-25 are withdrawn due to an Election/Restriction Requirement. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 16 is objected to because of the following informalities: In claim 16, lines 18-19, “the second memory, and” should be --the second memory cell, and--. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-2, 4-5 and 16-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding independent claim 1, the claim has been amended to recite that “the first source select transistor and the second source select transistor are controlled through an identical source select line shared by the first memory cell and the second memory cell”, and “the first cell string is disposed in a relatively outer portion among a plurality of cell strings and the second cell string is disposed in a relatively central portion among the plurality of cell strings”. However, the original disclosure does not disclose the combination now required by claim 1 in which the outer cell string and the central cell string include source select transistors controlled through an identical source select line shared by the outer and central memory cells. The identical source select line refers to embodiment of Figure 7 that concerns the adjacent cells MC11 and MC21. The outer/central cell string instead refers to embodiment of Figure 12 that concerns the cells MC11 and MC51. Figure 12 does not identify MC11 and MC51 as sharing an identical source select line. Instead, Figure 12 shows memory cells MC11-MC41 share a source select line SSL1 and memory cells MC51-MC81 share a source select line SSL2. Therefore, while the individual features of a shared sour select line and an outer/central memory cell pair separately in the disclosure, the disclosure does not reasonably convey possession of the claimed combination of those features. Claims 2 and 4-5 are rejected for the same reason because claims 2 and 4-5 depend on and incorporate the unsupported limitation of claim 1. Regarding claim 2, the claim further requires the outer first cell string and the central second cell string are disposed adjacent to each other. However, the original disclosure describes adjacent strings referring to embodiment of Figure 7 that concerns the adjacent cells MC11 and MC21. The outer/central cell string instead refers to embodiment of Figure 12 that concerns the cells MC11 and MC51. These MC11 and MC51 cells are not disposed adjacent to each other. The original disclosure does not describe a pair of strings that is simultaneously disposed in relatively outer and relatively central portions and adjacent to each other. Therefore, claim 2 constitutes a selection and combination of features from separate embodiments without adequate written description support for the claimed combination. Regarding independent claim 16, the claim has been amended to recite that “the identical source select line is shared by the first memory cell and the second memory cell”, and “the first cell string including the first memory cell is disposed in a relatively outer portion among the plurality of cell strings and the second cell string including the second memory cell is disposed in a relatively central portion among the plurality of cell strings”. However, the original disclosure does not disclose the combination now required by claim 16 in which the outer cell string and the central cell string include source select transistors controlled through an identical source select line shared by the outer and central memory cells. The identical source select line refers to embodiment of Figure 7 that concerns the adjacent cells MC11 and MC21. The outer/central cell string instead refers to embodiment of Figure 12 that concerns the cells MC11 and MC51. Figure 12 does not identify MC11 and MC51 as sharing an identical source select line. Instead, Figure 12 shows memory cells MC11-MC41 share a source select line SSL1 and memory cells MC51-MC81 share a source select line SSL2. Therefore, while the individual features of a shared sour select line and an outer/central memory cell pair separately in the disclosure, the disclosure does not reasonably convey possession of the claimed combination of those features. Claim 17 is rejected for the same reason because claim 17 depends on and incorporates the unsupported limitation of claim 16. Regarding claim 17, the claim further requires the outer first cell string and the central second cell string are disposed adjacent to each other. However, the original disclosure describes adjacent strings referring to embodiment of Figure 7 that concerns the adjacent cells MC11 and MC21. The outer/central cell string instead refers to embodiment of Figure 12 that concerns the cells MC11 and MC51. These MC11 and MC51 cells are not disposed adjacent to each other. The original disclosure does not describe a pair of strings that is simultaneously disposed in relatively outer and relatively central portions and adjacent to each other. Therefore, claim 17 constitutes a selection and combination of features from separate embodiments without adequate written description support for the claimed combination. Response to Arguments Applicant’s arguments with respect to claims 1-2, 4-5 and 16-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY H LUONG/Examiner, Art Unit 2825 /ANTHAN TRAN/Primary Examiner, Art Unit 2825
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Prosecution Timeline

Show 4 earlier events
Jan 26, 2026
Final Rejection mailed — §112
Mar 18, 2026
Applicant Interview (Telephonic)
Mar 18, 2026
Examiner Interview Summary
Apr 08, 2026
Request for Continued Examination
Apr 17, 2026
Response after Non-Final Action
May 28, 2026
Non-Final Rejection mailed — §112
Aug 27, 2026
Response Filed
Sep 23, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12737119
MEMORY DEVICE WITH ALTERNATE BIT LINE SENSING
2y 3m to grant Granted Sep 15, 2026
Patent 12725663
SEMICONDUCTOR MEMORY DEVICE PERFORMING PROGRAM OPERATION
2y 9m to grant Granted Sep 01, 2026
Patent 12725668
MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER, AND OPERATION METHOD
2y 1m to grant Granted Sep 01, 2026
Patent 12718864
COMPUTING SYSTEM PERFORMING DUTY CYCLE ADJUSTER TRAINING AND DUTY CYCLE ADJUSTER TRAINING METHOD THEREOF
2y 8m to grant Granted Aug 25, 2026
Patent 12718890
METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND MEMORY DEVICE
2y 0m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+7.7%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 41 resolved cases by this examiner. Grant probability derived from career allowance rate.

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