DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/07/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1- 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Clam 1 recites the limitation “a first surface” in the second line of the claim. It is unclear which element’s surface this limitation refers to.
Clam 1 recites the limitation “a second surface” in the third line of the claim. It is unclear which element’s surface this limitation refers to.
Claim 11 recites the limitation “at least one TSV” in the last line of the claim. It is unclear whether this limitation refers to “TSVs” in the second last line of the claim. It is recommended to replace “at least one TSV” with “at least one of the TSVs.”
Claim 16 recites the limitation “each conductive via” in the second last line of the claim. It is unclear whether this limitation refers to “a plurality of conductive vias” in the 4th and 5th lines of the claim. It is recommended to replace “each conductive via” with “each of the conductive vias.”
Claim 19 recites the limitation “the layers” in the 5th line of the claim. It is unclear whether this limitation refers “layers of metallization” in the 4th line of claim 19 or “buildup layers” in the second line of claim 16.
Claims 2-10, 12-15 and 17-20 are rejected because they depend on the rejected claims 1, 11 and 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paital et al. (US 20230085411 A1) in view of Gao et al. (US 20140264921 A1).
Regarding claim 1, Paital et al. teach a semiconductor die (108; Fig. 4J; [0067, 0021]), comprising: a first bond-pad (a portion of 202 below the bottom horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]) on a first surface (the bottom horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J, [0083]) to couple to a package substrate (104; Fig. 4J, [0066]); a second bond-pad (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]) on a second surface (the top horizontal surface of 108 from the left edge to the right edge), the second surface (the top horizontal surface of 108 from the left edge to the right edge) being opposite to the first surface (the bottom horizontal surface of 108 from the left edge to the right edge); a hole (the hole of 108 to hold 202; Figs. 4F, 4J; Fig. 2A) through the semiconductor die (108); a conductive pillar (the central portion of 202 in 108; Figs. 4F, 4J, [0091]) within the hole (the hole of 108 to hold 202; Figs. 4F, 4J), the conductive pillar (the central portion of 202 in 108) coupled to the first bond-pad (a portion of 202 below the bottom horizontal surface of 108 from the left edge to the right edge) and the second bond-pad (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge); and pathways (306/308; Figs. 4G and 4J; [0077]) conductively coupling at least two integrated circuit (IC) dies (112, 114; Figs. 4J and 2; [0074]) proximate (interpreted as “close”, based on the 2a definition of “very near : close” of https://www.merriam-webster.com/dictionary/proximate) to the second surface (the top horizontal surface of 108 from the left edge to the right edge).
Paital et al. do not teach a conductive pillar separated from sidewalls of the hole by an air gap.
In the same field of endeavor of electronic packaging, Gao et al. teach a conductive pillar (the central portion of 124; Fig. 7, [0027]) separated from sidewalls of the hole (110; Fig. 4, [0026]) by an air gap (127; Fig. 7, [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the conductive pillar and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 2, Paital et al. teach the semiconductor die of claim 1, wherein the first bond-pad (a portion of 202 below the bottom horizontal surface of 108 from the left edge to the right edge) and the second bond-pad (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J) are wider than the hole (the hole of 108 to hold 202; Figs. 4F, 4J).
Regarding claim 3, Paital et al. teach the semiconductor die of claim 1, wherein the first bond-pad (a portion of 202 below the bottom horizontal surface of 108 from the left edge to the right edge) is directly coupled to an interconnect (126; Fig. 4J, [0073]) of one of the IC dies (112, 114; see Fig. 4J).
Regarding claim 4, Paital et al. teach the semiconductor die of claim 1, wherein the second bond-pad (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge) is directly coupled to an interconnect (320; Fig. 4J, [0086]) of the package substrate (104; see Fig. 4J).
Regarding claim 5, Paital et al. teach the semiconductor die of claim 1, wherein the semiconductor die (108) is within a cavity (106; Fig. 4E and 4J, [0067]) in the package substrate (104; Fig. 4J).
Regarding claim 6, Paital et al. teach the semiconductor die of claim 1, wherein: the conductive pillar (the central portion of 202 in 108) has a first width (the upper width of the central portion of 202 in 108) proximate (close) to the first bond-pad (a portion of 202 below the bottom horizontal surface of 108 from the left edge to the right edge) and a second width (218) proximate (close) to the second bond-pad (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J).
Paital et al. do not teach the first width is larger than the second width.
In the same field of endeavor of electronic packaging, Gao et al. teach the first width (the horizontal width of 124 at the level of the top surface of 108; Fig. 8) is larger than the second width (the horizontal width of 124 in the opening of 136; Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to replace the semiconductor die 108 of Paital et al. with the semiconductor chip 102/104/108/120/122/124/141/127/136/138/140 of Fig. 8 of Gao et al., because the semiconductor chip of Fig. 8 of Gao et al. includes a TSV having the air gap which can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 9, Paital et al. teach the semiconductor die of claim 1, wherein: the semiconductor die (108) is coupled to the IC dies (112, 114) by a first interconnect (a portion of the left 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]) and a second interconnect (a portion of the right 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]), the first interconnect (a portion of the left 202 above the top horizontal surface of 108 from the left edge to the right edge) is physically coupled to the conductive pillar (the central portion of the left 202 in 108), and the second interconnect (a portion of the right 202 above the top horizontal surface of 108 from the left edge to the right edge) is physically coupled to the pathways (306/308 in Fig. 4J).
Regarding claim 10, Paital et al. teach the semiconductor die of claim 1, wherein the pathways (306/308) comprise conductive traces (308; Figs. 4G and 4J, [0077]) and conductive vias (306; Figs. 4G and 4J, [0077]) in interlayer dielectric (ILD) material (122; Figs. 4G and 4J, [0071]).
Regarding claim 11, Paital et al. teach an integrated circuit (IC) package, comprising: a package substrate (104; Fig. 4J, [0066]) having a surface (the top surface of 104) with a blind cavity (106; Fig. 4E and 4J, [0067]) extending partially through the package substrate (104) from the surface (the top surface of 104); a plurality of IC dies (112, 114; Figs. 4J and 2; [0074]) attached to the surface (the top surface of 104) of the package substrate (104); and a bridge die (108; Fig. 4J; [0067, 0021]) in the blind cavity (106) attached to the plurality of IC dies (112, 114), the bridge die (108) comprising: conductive pathways (a portion of 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]) conductively coupling at least a pair of IC dies (112, 114) in the plurality if IC dies (112, 114); through-silicon vias (TSVs) (the central portion of 202 in 108; Figs. 4F, 4J, [0091]) extending through a thickness of the bridge die (108).
Paital et al. do not teach an air gap around at least one TSV.
In the same field of endeavor of electronic packaging, Gao et al. teach an air gap (127; Fig. 7, [0030]) around at least one TSV (the central portion of 124; Fig. 7, [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the TSV conductor and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 12, Paital et al. teach the IC package of claim 11, wherein: the TSV (the central portion of 202 in 108) is in a hole (the hole of 108 to hold 202; Figs. 4F, 4J), the hole (the hole of 108 to hold 202; Figs. 4F, 4J) has substantially parallel sidewalls perpendicular to the surface (the top surface of 104).
Paital et al. do not teach the air gap is between the TSV and the sidewalls.
In the same field of endeavor of electronic packaging, Gao et al. teach the air gap (127; Fig. 7, [0030]) is between the TSV (the central portion of 124; Fig. 7, [0027]) and the sidewalls (the sidewalls of 110; Fig. 4, [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the TSV conductor and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 13, Paital et al. teach the IC package of claim 11, wherein: the plurality of IC dies (112, 114) is directly coupled to the bridge die (108) by at least first interconnects (126s; Fig. 4J, [0074]) and second interconnects (portions of 202 above the top horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]), and the first interconnects (126s) are larger than the second interconnects (portions of 202 above the top horizontal surface of 108 from the left edge to the right edge; see Fig. 2J).
Regarding claim 14, Paital et al. teach the IC package of claim 13, wherein the second interconnects (portions of 202 above the top horizontal surface of 108 from the left edge to the right edge; see Fig. 2J) are similar in size (the horizontal width) to the first interconnects (126s).
Regarding claim 15, Paital et al. teach the IC package of claim 13, wherein: the bridge die (108) is directly coupled to the package substrate (104) by third interconnects (portions of 202 below the bottom horizontal surface of 108 from the left edge to the right edge; Figs. 4F and 4J; [0091]), and the third interconnects (portions of 202 below the bottom horizontal surface of 108 from the left edge to the right edge) are similar in size (the horizontal width) to the first interconnects (126s; see Fig. 4J).
Regarding claim 16, Paital et al. teach a package substrate (104), comprising: buildup layers (400/302/408 in Fig. 4E, i.e. 104 in Fig. 4J; [0083, 0077]); a cavity (106; Fig. 4E and 4J, [0067]) in the buildup layers (104); and a semiconductor die (108) in the cavity (106; see Fig. 4F), the semiconductor die (108) comprising a plurality of conductive vias (the central portion of 202s in 108) proximate (close) to a periphery (the top outer surface) of the semiconductor die (108), wherein: each conductive via (the central portion of 202 in 108) extends through a thickness of the semiconductor die (108; see Fig. 4J).
Paital et al. do not teach an air gap surrounds each conductive via .
In the same field of endeavor of electronic packaging, Gao et al. teach an air gap (127; Fig. 7, [0030]) surrounds each conductive via (the central portion of 124; Fig. 7, [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the TSV conductor and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 17, Paital et al. teach the package substrate of claim 16.
Paital et al. do not teach wherein: each air gap is capped by a bond-pad on either end of the air gap, and the corresponding conductive via within the air gap is directly coupled to the bond-pads on either end of the air gap.
In the same field of endeavor of electronic packaging, Gao et al. teach wherein: each air gap (127; Fig. 7, [0030]) is capped by a bond-pad (a portion of 122/124 above the top horizontal surface of 108 from the left edge to the right edge; Fig. 7, [0027]) on either end of the air gap (the top end of 127), and the corresponding conductive via (a portion of 122/124 inside 127; Fig. 7, [0027]) within the air gap (127) is directly coupled to the bond-pads (a portion of 122/124 above the top horizontal surface of 108 from the left edge to the right edge) on either end of the air gap (the top end of 127).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the TSV conductor and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 18, Paital et al. teach the package substrate of claim 17.
Paital et al. do not teach wherein the bond-pads are wider than the air gap.
In the same field of endeavor of electronic packaging, Gao et al. teach wherein the bond-pads (a portion of 122/124 above the top horizontal surface of 108 from the left edge to the right edge) are wider than the air gap (127; see Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to include the air gap between the TSV conductor and the sidewalls of the hole of Paital et al., because the air gap can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 19, Paital et al. teach the package substrate of claim 16, wherein: the semiconductor die (108) comprises: a substrate ([0068]) including silicon ([0068]); layers of metallization (metallization layers; [0068]) including conductive traces ([0068]); interlayer dielectric (ILD) material ([0068]).
Paital et al. do not teach interlayer dielectric (ILD) material between the layers and in the layers between the conductive traces; and conductive vias through the ILD material, and the air gap around each conductive via extends through the substrate and the ILD material.
In the same field of endeavor of electronic packaging, Gao et al. teach interlayer dielectric (ILD) material (108 of silicon nitride; Fig. 8, [0025]) between the layers (102/104; Fig. 8, [0023]) and in the layers (102/104) between the conductive traces (122/124; Fig. 8, [0027]); and conductive vias (a portion of 122/124 inside 127; Fig. 8, [0027]) through the ILD material (108), and the air gap (127) around each conductive via (a portion of 122/124 inside 127) extends through the substrate (102; Fig. 8, [0023]) and the ILD material (108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Paital et al. and Gao et al., and to replace the semiconductor die 108 of Paital et al. with the semiconductor chip 102/104/108/120/122/124/141/127/136/138/140 of Fig. 8 of Gao et al., because the semiconductor chip of Fig. 8 of Gao et al. includes a TSV having the air gap which can reduce parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and also reduce mechanical stress in the silicon substrate surrounding the TSV conductor as taught by Gao et al. ([0009] of Gao et al.).
Regarding claim 20, Paital et al. teach the package substrate of claim 16, wherein: the semiconductor die (108) is coupled to interconnects (320; Fig. 4I, 4J, [0086]) at a bottom of the cavity (106), and each interconnect (320) is directly coupled to one of the conductive vias (the central portion of 202s in 108; Figs. 4I, 4J).
Conclusion
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 9/30/2026
