DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/17/2023, 08/07/2024 were filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al., U.S. Pub. No. 2024/0196631.
Regarding claim 13, Chen discloses a memory device, comprising:
a peripheral substrate 430 comprising a page buffer 104 [0032],
an array substrate (wafer 410) comprising an array 410 [0041],
a high voltage processing substrate 420 comprising a high voltage processing circuit [0042], wherein the array substrate 410, the peripheral substrate 430, and the high voltage processing substrate 420 are stacked on each other (Fig. 4), and the peripheral substrate does not have any high voltage processing circuit, [0039]-[0042].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., U.S. Pub. No. 2024/0196631.
Regarding claim 1, Chen discloses a memory device, comprising:
a peripheral substrate 430 comprising a page buffer 104 [0032],
an array substrate (wafer 410) comprising an array 410 [0041],
a high voltage processing substrate 420 comprising a high voltage processing circuit [0042], wherein the array substrate 410, the peripheral substrate 430, and the high voltage processing substrate 420 are stacked on each other (Fig. 4), and the peripheral substrate does not have any high voltage processing circuit, [0039]-[0042].
Chen fails to disclose a first circuit distribution area of the first high voltage processing circuit account for less than 10% of the peripheral substrate area. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 2, Chen discloses a second high voltage processing circuit (one of the high voltage circuits) but fails to disclose a second circuit distribution area of the second high voltage processing circuit accounts for less than 1% of the array substrate area. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 3, Chen discloses wherein the array substrate, the peripheral substrate and the high voltage processing substrate are stacked on each other.
Regarding claims 4-7, 14-15, Chen discloses the high voltage processing substate comprises a low voltage input but Chen fails to disclose a low voltage input is configured to receive a voltage less than 5V, and the high voltage input to receive a voltage equal to or higher than 5V. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 8, Chen discloses wherein one of the peripheral substrate and the array substrate comprises at least one conductive via and electrically connected to the other of the peripheral substrate and the array substrate [0051] (Fig. 4).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., U.S. Pub. No. 2024/0196631, in view of Lee et al., U.S Pub. No. 2022/0085048.
Regarding claim 16, Chen discloses a memory device, comprising:
a peripheral substrate 430 comprising a page buffer 104 [0032],
an array substrate (wafer 410) comprising an array 410 [0041],
a high voltage processing substrate 420 comprising a high voltage processing circuit [0042], wherein the array substrate 410 and the peripheral substrate 430 are stacked on each other (Fig. 4), and the high voltage processing substrate 420 are stacked on the layer 421 (Fig. 4), and the peripheral substrate does not have any high voltage processing circuit, [0039]-[0042].
Chen fails to disclose a circuit board, and wherein the array substrate and the peripheral substrate are stacked on the circuit board, and the high voltage processing substrate is disposed on the circuit board. Lee discloses a circuit board 2001 and electronic elements are located on the circuit board (many electric elements related to memory on top of circuit board 2001 in Fig. 12). It would have been obvious to one having ordinary skill to have a circuit board as disclosed in Lee in the device of Chen in order for the array substrate, the peripheral substrate, and the high voltage processing substrate being stacked on the circuit board so that electricity can flow, electrical signals are guided and the device can work.
Still regarding claim 16, Chen fails to disclose a high voltage processing circuit area of the high voltage processing circuit accounts for greater than 90% of the high voltage processing substrate area. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 18, Chen fails to mention wherein a high voltage processing substrate is disposed on the circuit board with a contact. Lee discloses a memory substrate or chip 2200 disposed on the circuit board. 2100 (Fig. 21). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the high voltage processing substrate of Chen’s device disposed on the circuit board with a contact of Lee’s device so that electricity can flow, electrical signals are guided and the device can work.
Claims 9, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., U.S. Pub. No. 2024/0196631, in view of Van Den Hoek, U.S. Pub. No. 2020/0381411.
Regarding claims 9, 17, Chen fails to disclose the memory comprising a solder wire connecting the high voltage processing substrate with the peripheral substrate.
Van Den Hoek discloses a solder wire 90 connecting the two substrates (Fig. 4A, 6A, 6B). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have solder wire to bond the two substrates in order form a low-resistance conductive oath between two substrates to prove reliable current flow, stable long term performance, provide good vibration resistance, and durable under normal operating stress. Still regarding claim 9, Chen fails to disclose high voltage processing substrate is smaller than the peripheral substrate area. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations having limitations of claim 1, further comprising: a circuit board, a high voltage processing substrate, wherein the peripheral substrate and the high voltage processing substrate are disposed on the circuit board side by side.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
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/THAO P LE/Primary Examiner, Art Unit 2818