Prosecution Insights
Last updated: August 17, 2026
Application No. 18/451,197

SEMICONDUCTOR PACKAGE

Final Rejection §103
Filed
Aug 17, 2023
Priority
Nov 09, 2022 — RE 10-2022-0148407
Examiner
ZARNEKE, DAVID A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
576 granted / 813 resolved
+2.8% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
63.5%
+23.5% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
4.2%
-35.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 813 resolved cases

Office Action

§103
DETAILED ACTION Response to Arguments Regarding the rejection over Park, Applicant’s arguments, see the claim amendments filed 5/22/26, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below. With respect to the rejection over Keeth, Applicant’s arguments, see the claim amendments filed 5/22/26, have been fully considered and are persuasive. Therefore it has been withdrawn. Claim Rejections - 35 USC § 103 Claims 1-3, 5-18 and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Park et al., US 2021/0407949, in view of Gluschenkov et al., US 8,237,278. The applied reference has a common assignee but no common inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Though the Park fails to specify the shape, namely rectangular, of the second upper bump pad, it would have been obvious to one of ordinary skill in the art at the time of the invention to use rectangular second upper bump pads in the invention of Park because changes in shape are within the ordinary level of skill in the art (MPEP 2144.04 IV). Regarding claim 1, Park (see marked up figure 2 below) teaches a semiconductor package, comprising: a first semiconductor chip including, a circuit layer 120 on a first surface 100L of a first substrate 110, first through silicon vias 150 passing through the first substrate 110, first lower bump pads 170 on the circuit layer 120 on the first substrate 110, each of the first lower bump pads 170 connected to a corresponding one of the first through silicon vias 150, and a first upper bump pad 1 and a second upper bump pad 180/185 on a second surface 100U of the first substrate 110, the second surface 100U opposite to the first surface 100L of the first substrate 110, each of the first upper bump pad 1 and the second upper bump pad 1/180/185 connected to a corresponding one of the first through silicon vias 150; a second semiconductor chip 210 including, a circuit layer 220 on a first surface 200L of a second substrate 210, and second lower bump pads 3/270/275 on the circuit layer 220 on the second substrate 210; a first solder bump 2 between the first upper bump pad 1 and the second lower bump pad 3 to bond the first upper bump pad 1 and the second lower bump pad 3; and a plurality of second solder bumps 195/290 between the second upper bump pad 270/275 and the second lower bump pads 180/185 to bond the second upper bump pad 270/275 and the second lower bump pads 180/185, wherein the plurality of second solder bumps 195/290 are spaced apart from each other on the second upper bump pad 180/185; and wherein the first upper bump pad 1 and the second upper bump pad 180/185 have a same stacked structure. PNG media_image1.png 564 896 media_image1.png Greyscale Though Park fails to teach the second bump pad has a rectangular shape contacting the plurality of second solder bumps, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a rectangular bump pad in the invention of Park because changes in size, shape or proportion are within the ordinary level of skill in the art (MPEP 2144.04 IV). The specification does not state any criticality for this shape and given it is an elongated pad a skilled artisan would think to use a rectangle bump pad as the shape for that elongated bump pad. Also, Park fails to teach the first bump pad and the second bump pad have a same stacked structure. Gluschenkov (see marked up figure 1A below) teaches the first bump pad 1 and the second bump pad 2 have a same stacked structure. PNG media_image2.png 259 667 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art at the time of the invention to use the bumps having the same stacked structure of Gluschenkov in the invention of Park because Gluschenkov teaches an equivalent bump pad structure. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Park does not give any criticality to the stacked structure and also shows several embodiments (figures 3 & 4B) therefore it is open to variations and a skilled artisan knows that making the stacked structures the same would decrease costs and production time. With respect to claim 2, Park (see marked up figure 2 above) teaches an upper surface area of the second upper bump pad 180/185 is greater than an upper surface area of the first upper bump pad 1. As to claim 3, Park (see marked up figure 2 above) teaches the second upper bump pad 180/185 is shaped as a line in one direction to contact lower portions of the second solder bumps 195/290, and the second solder bumps 195/290 are spaced apart from each other in the one direction. In re claim 5, park (paragraphs 0039 & 0043) teaches each of the first upper bump pad and the second upper bump pad includes at least one of copper, tin (Sn), nickel (Ni), gold (Au), or silver (Ag). Concerning claim 6, Park (see marked up figure 2 above) teaches one of first solder bumps 2 is bonded to one of the first upper bump pads 1. Pertaining to claim 7, Park teaches the second solder bumps include signal transmission bumps 195/290 and though Park fails to specifically teach thermal path bumps, it would have been obvious to one of ordinary skill in the art at the time of the invention to use thermal path bumps in the invention of Park because thermal path bumps are conventionally known and used in the art to remove heat from the device. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In claim 8, wherein the plurality of the second lower bump pads 270/275 face the second upper bump pad 180/185 in a vertical direction, and one of the plurality of the second lower bump pads 270 faces one of the first through silicon vias 150. Regarding claim 9, wherein the second lower bump pads 270/275 face the plurality of the second upper bump pad 180/185 in a vertical direction, and some of the plurality of the second lower bump pads 185 do not face the first through silicon vias 150 . With respect to claim 10, Park (figure 13 & marked up figures 2 above) semiconductor package, comprising: a buffer die 20; a plurality of first semiconductor chips 100/200/300 sequentially stacked on the buffer die 20; and a sealing member 34 covering the first semiconductor chips 100/200/300 on the buffer die 20, wherein each of the first semiconductor chips 100/200/300 includes, a circuit layer 120 on a first surface 100L of a first substrate 100, first through silicon vias 150 passing through the first substrate 100, lower bump pads 170 on the circuit layer 120 on the first substrate 100, each of the lower bump pads 170 connected to a corresponding one of the first through silicon vias 150, a first bump pad 1 and a second bump pad 180/185 on a second surface 100U of the first substrate 100, the second surface 100U opposite to the first surface 100L of the first substrate 100, wherein an upper surface area of the second bump pad 180/185 is greater than an upper surface area of the first bump pad 1, a first solder bump 2 between the first bump pad 1 and one of the lower bump pads 3 of one of the plurality of first semiconductor chips 100 above the second surface 100U, and a plurality of second solder bumps 195/290 between the second bump pad 180/185 and lower bump pads 170 of the one of the plurality of first semiconductor chips 100 above the second surface 100U. Though Park fails to teach the second bump pad has a rectangular shape contacting the plurality of second solder bumps, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a rectangular bump pad in the invention of Park because changes in size, shape or proportion are within the ordinary level of skill in the art (MPEP 2144.04 IV). The specification does not state any criticality for this shape and given it is an elongated pad a skilled artisan would think to use a rectangle bump pad as the shape for that elongated bump pad. Also, Park fails to teach the first bump pad and the second bump pad have a same stacked structure. Gluschenkov (see marked up figure 1A below) teaches the first bump pad 1 and the second bump pad 2 have a same stacked structure. PNG media_image2.png 259 667 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art at the time of the invention to use the bumps having the same stacked structure of Gluschenkov in the invention of Park because Gluschenkov teaches an equivalent bump pad structure. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Park does not give any criticality to the stacked structure and also shows several embodiments (figures 3 & 4B) therefore it is open to variations and a skilled artisan knows that making the stacked structures the same would decrease costs and production time. As to claim 11, Park (see marked up figure 2 above) teaches the plurality of second solder bumps 195/290 are spaced apart from each other on the second bump pad 180/185. In re claim 12, Park (see marked up figure 2 above) teaches the second solder bumps 195/270 include a signal transmission bump 270 and a thermal path bump 195, the signal transmission bump 270 faces one of the first through silicon vias 150 of one of the plurality of first semiconductor chips 110 below the signal transmission bump 270 in a vertical direction, and the thermal path bump 195 does not face one of the first through silicon vias 150 of the one of the plurality of first semiconductor chips 110 below the thermal path bump 195 in the vertical direction. Though Park fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path. Concerning claim 13, Park (see marked up figure 2 above) teaches the first bump pad 1 of a first one of the plurality of first semiconductor chips 110 is aligned with one of the lower bump pads 3 of a second one of the plurality of first semiconductor chips 210 above the first one of the plurality of first semiconductor chips 110 in a vertical direction. Pertaining to claim 14, Park (see marked up figure 2 above) teaches the second bump pad 180/185 of a first one of the plurality of first semiconductor chips 110 faces a plurality of lower bump pads 270/275 of a second one of the plurality of first semiconductor chips 210 above the first one of the plurality of first semiconductor chips 110 in a vertical direction. In claim 15, wherein each of the first solder bumps 2 and the second solder bumps 195/290 are matched 1:1 with one lower bump pad 180/185/1. Regarding claim 16, Park (paragraphs 0039 & 0043) teaches each of the first and second bump pads includes at least one of copper, tin (Sn), nickel (Ni), gold (Au) or silver (Ag). With respect to claim 17, Park (see marked up figure 2 above) teaches a semiconductor package, comprising: a first semiconductor chip 110 including, lower bump pads 190 on a first surface 100L of a first substrate 110, and a first upper bump pad 1 and a second upper bump pad 180/185 on a second surface 100U of the first substrate 110, the second surface 100U opposite to the first surface 100L of the first substrate 110, wherein an upper surface area of the second upper bump pad 180/185 is greater than an upper surface area of the first upper bump pad 1; solder bumps 2/195/290 on each of the first upper bump pad 1 and second upper bump pad 180/185; and a second semiconductor chip 210 bonded on the first semiconductor chip 110 by the solder bumps 2/195/290, wherein one of the solder bumps 2 is on the first upper bump pad 1, and a plurality of the solder bumps 195/290 are on the second upper bump pad 180/185. Though Park fails to teach the second bump pad has a rectangular shape contacting the plurality of second solder bumps, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a rectangular bump pad in the invention of Park because changes in size, shape or proportion are within the ordinary level of skill in the art (MPEP 2144.04 IV). The specification does not state any criticality for this shape and given it is an elongated pad a skilled artisan would think to use a rectangle bump pad as the shape for that elongated bump pad. Also, Park fails to teach the first bump pad and the second bump pad have a same stacked structure. Gluschenkov (see marked up figure 1A below) teaches the first bump pad 1 and the second bump pad 2 have a same stacked structure. PNG media_image2.png 259 667 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art at the time of the invention to use the bumps having the same stacked structure of Gluschenkov in the invention of Park because Gluschenkov teaches an equivalent bump pad structure. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). Park does not give any criticality to the stacked structure and also shows several embodiments (figures 3 & 4B) therefore it is open to variations and a skilled artisan knows that making the stacked structures the same would decrease costs and production time. As to claim 18, Park (figure 1) teaches the second upper bump pad 180/185 is shaped as a line extending in one direction to contact lower portions of the solder bumps 195/290, and the solder bumps 195/290 are spaced apart from each other in the one direction. In re claim 20, Park (see marked up figure 2 above) teaches the solder bumps 1/195/290 include a plurality of second solder bumps 195/290, and the second solder bumps 195/290 include a signal transmission bump 290 and a thermal path bump 185. Though Park fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path. Claim(s) 4 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US 2021/0407949, in view of Gluschenkov et al., US 8,237,278, as applied to claims 1, and 17 respectively above, in view of Chandolu, US 10,192,952. Concerning claims 4 and 19, Park fails to teach at least some of the second solder bumps are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction, it would have been obvious to one of ordinary skill in the art at the time of the invention to a rectangular shape with solder bumps in first and second directions in the invention of Park because teaches Chandolu (see marked up figure 3 below) teaches an upper surface of the second upper bump pad 330 has a rectangular shape to contact the second solder bumps 334, at least some of the second solder bumps 334 are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction. It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder bump array of Chandolu in the invention of Park because Chandolu teaches it prevents electrical shorting (column 6, lines 28-31) and open circuits (column 1, lines 37-40). PNG media_image3.png 456 668 media_image3.png Greyscale Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry should be directed to DAVID A ZARNEKE at (571)272-1937. If attempts to reach the examiner are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax number is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/ patent-center for more information about Patent Center and https://www.uspto.gov/ patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 7/17/26
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Prosecution Timeline

Show 2 earlier events
Mar 30, 2026
Interview Requested
Apr 10, 2026
Applicant Interview (Telephonic)
Apr 10, 2026
Examiner Interview Summary
May 22, 2026
Response Filed
Jul 21, 2026
Final Rejection mailed — §103
Aug 08, 2026
Interview Requested
Aug 14, 2026
Applicant Interview (Telephonic)
Aug 14, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
82%
With Interview (+10.8%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 813 resolved cases by this examiner. Grant probability derived from career allowance rate.

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