DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I and Species 1b and 2c, corresponding to claims 1-9, in the reply filed on 12/18/25 is acknowledged. The traversal is on the ground(s) that the search doesn’t require a serious burden, there are only 3 independent claims and 20 total claims, and the disclosure doesn’t allege the invention groups are mutually exclusive.
This is found persuasive and the restriction between groups I, II and III is withdrawn. However the species restriction is retained.
The species requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim(s) 1-3, 5-18, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Park et al., US 2021/0407949.
Regarding claim 1, Park (see marked up figure 2 below) teaches a semiconductor package, comprising:
a first semiconductor chip including,
a circuit layer 120 on a first surface 100L of a first substrate 110,
first through silicon vias 150 passing through the first substrate 110,
first lower bump pads 170 on the circuit layer 120 on the first substrate 110, each of the first lower bump pads 170 connected to a corresponding one of the first through silicon vias 150, and
a first upper bump pad 1 and a second upper bump pad 180/185 on a second surface 100U of the first substrate 110, the second surface 100U opposite to the first surface 100L of the first substrate 110, each of the first upper bump pad 1 and the second upper bump pad 1/180/185 connected to a corresponding one of the first through silicon vias 150;
a second semiconductor chip 210 including,
a circuit layer 220 on a first surface 200L of a second substrate 210, and
second lower bump pads 3/270/275 on the circuit layer 220 on the second substrate 210;
a first solder bump 2 between the first upper bump pad 1 and the second lower bump pad 3 to bond the first upper bump pad 1 and the second lower bump pad 3; and
a plurality of second solder bumps 195/290 between the second upper bump pad 270/275 and the second lower bump pads 180/185 to bond the second upper bump pad 270/275 and the second lower bump pads 180/185,
wherein the plurality of second solder bumps 195/290 are spaced apart from each other on the second upper bump pad 180/185.
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With respect to claim 2, Park (see marked up figure 2 above) teaches an upper surface area of the second upper bump pad 180/185 is greater than an upper surface area of the first upper bump pad 1.
As to claim 3, Park (see marked up figure 2 above) teaches the second upper bump pad 180/185 is shaped as a line in one direction to contact lower portions of the second solder bumps 195/290, and the second solder bumps 195/290 are spaced apart from each other in the one direction.
In re claim 5, park (paragraphs 0039 & 0043) teaches each of the first upper bump pad and the second upper bump pad includes at least one of copper, tin (Sn), nickel (Ni), gold (Au), or silver (Ag).
Concerning claim 6, Park (see marked up figure 2 above) teaches one of first solder bumps 2 is bonded to one of the first upper bump pads 1.
Pertaining to claim 7, Park teaches the second solder bumps include signal transmission bumps 195/290 and though Park fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
In claim 8, wherein the second lower bump pads 270/275 face the second upper bump pad 180/185 in a vertical direction, and one of the second lower bump pads 270 faces one of the first through silicon vias 150.
Regarding claim 9, wherein the second lower bump pads 270/275 face the second upper bump pad 180/185 in a vertical direction, and some of the second lower bump pads 185 do not face the first through silicon vias 150 .
With respect to claim 10, Park (figure 13 & marked up figures 2 above) semiconductor package, comprising:
a buffer die 20;
a plurality of first semiconductor chips 100/200/300 sequentially stacked on the buffer die 20; and
a sealing member 34 covering the first semiconductor chips 100/200/300 on the buffer die 20,
wherein each of the first semiconductor chips 100/200/300 includes,
a circuit layer 120 on a first surface 100L of a first substrate 100,
first through silicon vias 150 passing through the first substrate 100,
lower bump pads 170 on the circuit layer 120 on the first substrate 100, each of the lower bump pads 170 connected to a corresponding one of the first through silicon vias 150,
a first bump pad 1 and a second bump pad 180/185 on a second surface 100U of the first substrate 100, the second surface 100U opposite to the first surface 100L of the first substrate 100, wherein an upper surface area of the second bump pad 180/185 is greater than an upper surface area of the first bump pad 1,
a first solder bump 2 between the first bump pad 1 and one of the lower bump pads 3 of one of the plurality of first semiconductor chips 100 above the second surface 100U, and
a plurality of second solder bumps 195/290 between the second bump pad 180/185 and lower bump pads 170 of the one of the plurality of first semiconductor chips 100 above the second surface 100U.
As to claim 11, Park (see marked up figure 2 above) teaches the plurality of second solder bumps 195/290 are spaced apart from each other on the second bump pad 180/185.
In re claim 12, Park (see marked up figure 2 above) teaches the second solder bumps 195/270 include a signal transmission bump 270 and a thermal path bump 195, the signal transmission bump 270 faces one of the first through silicon vias 150 of one of the plurality of first semiconductor chips 110 below the signal transmission bump 270 in a vertical direction, and the thermal path bump 195 does not face one of the first through silicon vias 150 of the one of the plurality of first semiconductor chips 110 below the thermal path bump 195 in the vertical direction. Though Park fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
Concerning claim 13, Park (see marked up figure 2 above) teaches the first bump pad 1 of a first one of the plurality of first semiconductor chips 110 is aligned with the lower bump pad 3 of a second one of the plurality of first semiconductor chips 210 above the first one of the plurality of first semiconductor chips 110 in a vertical direction.
Pertaining to claim 14, Park (see marked up figure 2 above) teaches the second bump pad 180/185 of a first one of the plurality of first semiconductor chips 110 faces a plurality of lower bump pads 270/275 of a second one of the plurality of first semiconductor chips 210 above the first one of the plurality of first semiconductor chips 110 in a vertical direction.
In claim 15, wherein each of the first solder bumps 2 and the second solder bumps 195/290 are matched 1:1 with one lower bump pad 180/185/1.
Regarding claim 16, Park (paragraphs 0039 & 0043) teaches each of the first and second bump pads includes at least one of copper, tin (Sn), nickel (Ni), gold (Au) or silver (Ag).
With respect to claim 17, Park (see marked up figure 2 above) teaches a semiconductor package, comprising:
a first semiconductor chip 110 including,
lower bump pads 190 on a first surface 100L of a first substrate 110, and
a first upper bump pad 1 and a second upper bump pad 180/185 on a second surface 100U of the first substrate 110, the second surface 100U opposite to the first surface 100L of the first substrate 110, wherein an upper surface area of the second upper bump pad 180/185 is greater than an upper surface area of the first upper bump pad 1;
solder bumps 2/195/290 on each of the first upper bump pad 1 and second upper bump pad 180/185; and
a second semiconductor chip 210 bonded on the first semiconductor chip 110 by the solder bumps 2/195/290,
wherein one of the solder bumps 2 is on the first upper bump pad 1, and
a plurality of the solder bumps 195/290 are on the second upper bump pad 180/185.
As to claim 18, Park (figure 1) teaches the second upper bump pad 180/185 is shaped as a line extending in one direction to contact lower portions of the solder bumps 195/290, and the solder bumps 195/290 are spaced apart from each other in the one direction.
In re claim 20, Park (see marked up figure 2 above) teaches the solder bumps 1/195/290 include a plurality of second solder bumps 195/290, and the second solder bumps 195/290 include a signal transmission bump 290 and a thermal path bump 185. Though Park fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US 2021/0407949, as applied to claims 1 and 17 respectively above, in view of Chandolu, US 10,192,952.
Concerning claims 4 and 19, Park fails to teach an upper surface of the second upper bump pad has a rectangular shape to contact the second solder bumps, at least some of the second solder bumps are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction, it would have been obvious to one of ordinary skill in the art at the time of the invention to a rectangular shape with solder bumps in first and second directions in the invention of Park because teaches
Chandolu (see marked up figure 3 below) teaches an upper surface of the second upper bump pad 330 has a rectangular shape to contact the second solder bumps 334, at least some of the second solder bumps 334 are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder bump array of Chandolu in the invention of Park because Chandolu teaches it prevents electrical shorting (column 6, lines 28-31) and open circuits (column 1, lines 37-40).
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Rejections over Keeth, US 2020/0098730
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, 17, 18, and 20 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Keeth, US 2020/0098730.
Pertaining to claim 1, Keeth (see marked up figure 8:805-b below) teaches a semiconductor package, comprising:
a first semiconductor chip 850 including,
a circuit layer (paragraph 0082 states it is a memory die with a signal path therefore it inherently has a circuit layer) on a first surface (bottom) of a first substrate 850,
first through silicon vias 870 passing through the first substrate 850,
first lower bump pads 1 on the circuit layer on the first substrate 850, each of the first lower bump pads 1 connected to a corresponding one of the first through silicon vias 870, and
a first upper bump pad 2 and a second upper bump pad 880 on a second surface (top) of the first substrate 850, the second surface (top) opposite to the first surface (bottom) of the first substrate 850, each of the first upper bump pad 2 and the second upper bump pad 880 connected to a corresponding one of the first through silicon vias 870;
a second semiconductor chip 855 including,
a circuit layer (paragraph 0082 states it is a memory die with a signal path therefore it inherently has a circuit layer) on a first surface of a second substrate 855, and
second lower bump pads 3 on the circuit layer on the second substrate 855;
a first solder bump 4 between the first upper bump pad 2 and the second lower bump pad 3 to bond the first upper bump pad 2 and the second lower bump pad 3; and
a plurality of second solder bumps 5 between the second upper bump pad 880 and the second lower bump pads 3 to bond the second upper bump pad 880 and the second lower bump pads 3,
wherein the plurality of second solder bumps 5 are spaced apart from each other on the second upper bump pad 880.
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In claim 2, Keeth (see marked up figure 8:805-b above) teaches an upper surface area of the second upper bump pad 880 is greater than an upper surface area of the first upper bump pad 2.
Regarding claim 3, Keeth (see marked up figure 8:805-b above) teaches the second upper bump pad 880 is shaped as a line in one direction (paragraph 0082 states a lateral conductive path) to contact lower portions of the second solder bumps 5, and the second solder bumps 5 are spaced apart from each other in the one direction.
With respect to 6, Keeth (see marked up figure 8:805-b above) teaches one of first solder bumps 4 is bonded to one of the first upper bump pads 2.
As to claim 7, Keeth (see marked up figure 8:805-b below) teaches the second solder bumps 5 include signal transmission bumps 5 and thermal path bumps 5. Though Keeth fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
In re claim 8, Keeth (see marked up figure 8:805-b above) teaches the second lower bump pads 3 face the second upper bump pad 2 in a vertical direction, and one of the second lower bump pads 880 faces one of the first through silicon vias 870.
Concerning claim 9, Keeth (see marked up figure 8:805-b above) teaches the second lower bump pads 3 face the second upper bump pad 880 in a vertical direction, and some of the second lower bump pads 3 do not face the first through silicon vias 870.
Pertaining to claim 17, Keeth (see marked up figure 8:805-b above) teaches a semiconductor package, comprising:
a first semiconductor chip 850 including,
lower bump pads 1 on a first surface (bottom) of a first substrate 850, and
a first upper bump pad 2 and a second upper bump pad 880 on a second surface (top) of the first substrate 850, the second surface (top) opposite to the first surface (bottom) of the first substrate 850, wherein an upper surface area of the second upper bump pad 880 is greater than an upper surface area of the first upper bump pad 2;
solder bumps 875 on each of the first upper bump pad 2 and second upper bump pad 880; and
a second semiconductor chip 855 bonded on the first semiconductor chip 850 by the solder bumps 875,
wherein one of the solder bumps 875 is on the first upper bump pad 2, and
a plurality of the solder bumps 875 are on the second upper bump pad 880.
In claim 18, Keeth (see marked up figure 8:805-b above) teaches the second upper bump pad 880 is shaped as a line (paragraph 0082 states a lateral conductive path) extending in one direction to contact lower portions of the solder bumps 875, and the solder bumps 875 are spaced apart from each other in the one direction.
Regarding claim 20, Keeth (see marked up figure 8:805-b above) teaches the solder bumps 875 include a plurality of second solder bumps (875 on 880), and the second solder bumps (875 on 880) include a signal transmission bump 875 and a thermal path bump 875. Though Keeth fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
Claim(s) 4 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keeth, US 2020/0098730, as applied to claims 1 and 17 respectively above, in view of Chandolu, US 10,192,952.
Concerning claims 4 and 19, Keeth fails to teach an upper surface of the second upper bump pad has a rectangular shape to contact the second solder bumps, at least some of the second solder bumps are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction, it would have been obvious to one of ordinary skill in the art at the time of the invention to a rectangular shape with solder bumps in first and second directions in the invention of Park because teaches
Chandolu (see marked up figure 3 above) teaches an upper surface of the second upper bump pad 330 has a rectangular shape to contact the second solder bumps 334, at least some of the second solder bumps 334 are spaced apart from each other in a first direction, and at least some of the second solder bumps are spaced apart from each other in a second direction perpendicular to the first direction.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder bump array of Chandolu in the invention of Park because Chandolu teaches it prevents electrical shorting (column 6, lines 28-31) and open circuits (column 1, lines 37-40).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keeth, US 2020/0098730, as applied to claim 1 respectively above.
Pertaining to claim 5, though Keeth fails to teach each of the first and second bump pads includes at least one of copper, tin (Sn), nickel (Ni), gold (Au) or silver (Ag), it would have been obvious to one of ordinary skill in the art at the time of the invention to use these materials in the invention of Keeth because they are conventionally known and used bump pad materials The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Claim(s) 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keeth, US 2020/0098730, in view of Park et al., US 2021/0407949.
In claim 10, Keeth (figure 3 & see marked up figure 8:805-b above) teaches a semiconductor package, comprising:
a buffer die 311;
a plurality of first semiconductor chips 305a-h sequentially stacked on the buffer die 311; and
wherein each of the first semiconductor chips 850 includes,
a circuit layer (paragraph 0082 states it is a memory die with a signal path therefore it inherently has a circuit layer) on a first surface (bottom) of a first substrate 850,
first through silicon vias 870 passing through the first substrate 850,
lower bump pads 1 on the circuit layer on the first substrate 850, each of the lower bump pads 1 connected to a corresponding one of the first through silicon vias 870,
a first bump pad 2 and a second bump pad 880 on a second surface (top) of the first substrate 850, the second surface (top) opposite to the first surface (bottom) of the first substrate 850, wherein an upper surface area of the second bump pad 880 is greater than an upper surface area of the first bump pad 2,
a first solder bump 875 between the first bump pad 2 and one of the lower bump pads 3 of one of the plurality of first semiconductor chips 855 above the second surface, and
a plurality of second solder bumps 5 between the second bump pad 880 and lower bump pads 3 of the one of the plurality of first semiconductor chips 855 above the second surface.
Keeth fails to teach a sealing member covering the first semiconductor chips on the buffer die.
Park (figure 13) teaches a sealing member 34 covering the first semiconductor chips 100/200/300 on the buffer die 20.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the sealing member of Park in the invention of Keeth because a sealing member protects the first semiconductor chips 100/200/300 from environmental factors and provides mechanical strength. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 11, Keeth (see marked up figure 8:805-b above) teaches the plurality of second solder bumps 5 are spaced apart from each other on the second bump pad 880.
With respect to claim 12, Keeth (see marked up figure 8:805-b above) teaches the second solder bumps include a signal transmission bump (5 over 870) and a thermal path bump (offset 5), the signal transmission bump (5 over 870) faces one of the first through silicon vias 870 of one of the plurality of first semiconductor chips 850 below the signal transmission bump (5 over 870) in a vertical direction, and the thermal path bump (offset 5) does not face one of the first through silicon vias 870 of the one of the plurality of first semiconductor chips 850 below the thermal path bump (offset 5) in the vertical direction. Though Keeth fails to specifically teach thermal path bumps, bumps inherently are thermally conductive and therefore additional bumps inherently provide thermal path.
As to claim 13, Keeth (see marked up figure 8:805-b above) teaches the first bump pad 2 of a first one of the plurality of first semiconductor chips 850 is aligned with the lower bump pad 3 of a second one of the plurality of first semiconductor chips 855 above the first one of the plurality of first semiconductor chips 850 in a vertical direction.
In re claim 14, Keeth (see marked up figure 8:805-b above) teaches the second bump pad 880 of a first one of the plurality of first semiconductor chips 850 faces a plurality of lower bump pads 3 of a second one 855 of the plurality of first semiconductor chips above the first one of the plurality of first semiconductor chips 850 in a vertical direction.
Concerning claim 15, Keeth (see marked up figure 8:805-b above) teaches each of the first solder bumps 4 and the second solder bumps 875 are matched 1:1 with one lower bump pad 3.
Pertaining to claim 16, though Keeth fails to teach each of the first and second bump pads includes at least one of copper, tin (Sn), nickel (Ni), gold (Au) or silver (Ag), it would have been obvious to one of ordinary skill in the art at the time of the invention to use these materials in the invention of Keeth because they are conventionally known and used bump pad materials The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach inventions relevant to the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 2/19/26