DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 11-12, 15, and 190 are rejected under U.S.C. 103 as being unpatentable over Renzas et al.; US 11,276,727 B1; 06/2018 in view of MacLean et al.; US 2023/0187503 A1; 08/2021
Claim 1: Renzas discloses a method for preparing multi-superconducting material layers, comprising: depositing a first superconducting material layer ( Fig. 1C: superconducting material in first layer 130 ) on a substrate ( Fig. 1C: substrate 102 ), the first superconducting material layer ( Fig. 1C #130 ) being formed by covering a first superconducting material ( Col. 8 lines 62 – 66 the first layer 130 may be formed of niobium with compressive stress ) in a first target region range with a first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) in the first target region range ( as shown in Fig. 1C ); depositing a second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress ) on the substrate ( Fig. 1C #102 ) deposited with the first superconducting material layer ( Fig. 1C #130 ); covering the second superconducting material with a second hard mask ( as discussed above ); and performing etching treatment ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) on the second hard mask ( as discussed above ) and the second superconducting material ( as discussed above ) to obtain a second superconducting material layer ( Fig. 1C #132 ) formed by covering the second superconducting material ( as discussed above ) in a second target region range ( as shown in Fig. 1C ) with the second hard mask ( as discussed above ) in the second target region range ( as discussed above ).
Renzas does not appear to disclose the first target region range and the second target region range are separated.
However, MacLean teaches the first target region range and the second target region range are separated ( Fig. 3A target region 312 are separated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of MacLean with Renzas to implement the first target region range and the second target region range are separated because this approach allows independent selective deposition and patterning of different superconducting materials on the same substrate.
Claim 2: Renzas and MacLean disclose the method according to claim 1 ( as discussed above ).
Renzas teaches depositing the first superconducting material layer ( Fig. 1C #130 ) on the substrate ( Fig. 1C #102 ) comprises: depositing the first superconducting material ( Col. 8 lines 62 – 66 the first layer 130 may be formed of niobium with compressive stress ) on the substrate ( Fig. 1C #102 ); covering the first superconducting material ( as discussed above ) with the first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ); determining the first target region range ( Fig. 1C #130 ) in which the first superconducting material ( as discussed above ) is to retain on the substrate ( Fig. 1C #102 ); and etching away a first hard mask ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) of a first other region range ( Fig. 1C #118 ) in the first hard mask ( as discussed above ) and a superconducting material of the first other region range ( Fig. 1C #118 ) in the first superconducting material ( as discussed above ), respectively, wherein the first other region range ( Fig. 1C #118 ) is a region range on the substrate ( Fig. 1C #102 ) in addition to the first target region range ( Fig. 1C right side of substrate with layer #130 ).
Claim 3: Renzas and MacLean disclose the method according to claim 1 ( as discussed above ).
Renzas teaches performing etching treatment on the second hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) and the second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress ) to obtain a second superconducting material layer ( Fig. 1C #132 ) formed by covering ( as discussed above ) the second superconducting material ( as discussed above ) in a second target region range ( Fig. 1C right surface of substrate with layer #132 ) with the second hard mask ( as discussed above ) in the second target region range comprises: etching away a second hard mask ( as discussed above) of a second other region range ( Fig. 1C #118 region ) in the second hard mask ( as discussed above ) and a superconducting material ( as discussed above ) of the second other region range ( Fig. 1C #118 region ) in the second superconducting material ( as discussed above), respectively, wherein the second other region range ( Fig. 1C #118 region ) is a region range on the substrate ( Fig. 1C #102 ) in addition to the second target region range ( Fig. 1C right side of substrate ).
Claim 4: Renzas and MacLean disclose the method according to claim 1 ( as discussed above ).
Renzas teaches after performing etching treatment ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) on the second hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) and the second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress ) to obtain a second superconducting material layer ( Fig. 1C #132 ) formed by covering the second superconducting material ( as discussed above ) in a second target region range ( Fig. 1C right side of substrate ) with the second hard mask ( as discussed above) in the second target region range ( Fig. 1C right side of substrate ), the method further comprises: etching away ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) the first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) on the first superconducting material layer ( Fig. 1C #130 ) and the second hard mask ( as discussed above ) on the second superconducting material layer ( Fig. 1C #132 ) to obtain a first target superconducting device ( Col 17. lines 8 – 11 FIG. 3 presents a schematic diagram of an example method 300 for fabricating a quantum circuit on a substrate 302 having a superconducting via 304 and a first surface 306 that is fully uncovered ) on the substrate ( Fig. 1C #102 ).
Claim 5: Renzas and MacLean disclose the method according to claim 4 ( as discussed above).
Renzas teaches etching away the first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) on the first superconducting material layer ( Fig. 1C #130 ) and the second hard mask ( as discussed above ) on the second superconducting material layer ( Fig. 1C #132 ) to obtain a first target superconducting device ( Col 17. lines 8 – 11 FIG. 3 presents a schematic diagram of an example method 300 for fabricating a quantum circuit on a substrate 302 having a superconducting via 304 and a first surface 306 that is fully uncovered ) on the substrate ( Fig. 1C #102 ) comprises: etching away the first hard mask ( as discussed above ) on the first superconducting material layer ( Fig. 1C #130 ) and the second hard mask ( as discussed above ) on the second superconducting material layer ( Fig. 1C #132 ) by using a dilute hydrofluoric acid (DHF) solution ( Col. 15 lines 23 – 26 In another example, the patterned etch-stop layer may be formed of a silicon oxynitride material (i.e., Si.sub.xO.sub.yN.sub.z) and the solution may be a buffered etch solution, such as a buffered oxide etch (BOE) solution; DHF is part of a BOE solution ) to obtain the first target superconducting device ( Col 17. lines 8 – 11 FIG. 3 presents a schematic diagram of an example method 300 for fabricating a quantum circuit on a substrate 302 having a superconducting via 304 and a first surface 306 that is fully uncovered ) on the substrate ( Fig. 1C #102 ).
Claim 11: Renzas and MacLean disclose the method according to claim 2 ( as discussed above ).
Renzas teaches the first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) of the first other region range ( Fig. 1C#118 region for layer #130 ) in the first hard mask ( as discussed above ) is etched away in a manner combining photolithography ( Col. 15 lines 20 – 23 For example, the patterned etch-stop layer may be formed of photoresist and the solution may be a solvent capable of dissolving the photoresist ) and dry etching ( Col. 22 lines 6 – 8 Other types of subtractive processes are also possible for removing portions of the dry photoresist (i.e., chemical etches, milling, etc.) ); and the superconducting material of the first other region range ( Fig. 1C #118 region for layer #130 ) in the first superconducting material ( Col. 8 lines 62 – 66 the first layer 130 may be formed of niobium with compressive stress ) is etched away in a wet etching manner ( Col. 25 lines 36 – 39 The support layer may be deposited, in some instances, using an etching process) to reveal the superconducting metal layer ( Fig. 1C #130 ) on the other side of the substrate ( Fig. 1C #102 ).
Claim 12: Renzas and MacLean disclose the method according to claim 3 ( as discussed above).
Renzas teaches the second hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) of the second other region range ( Fig. 1C #118 for the #132 layer ) in the second hard mask ( as discussed above ) is etched away in a manner combining photolithography ( Col. 15 lines 20 – 23 For example, the patterned etch-stop layer may be formed of photoresist and the solution may be a solvent capable of dissolving the photoresist ) and dry etching ( Col. 22 lines 6 – 8 Other types of subtractive processes are also possible for removing portions of the dry photoresist (i.e., chemical etches, milling, etc.) ); and the superconducting material of the second other region range ( Fig. 1C #118 region for layer #132 ) in the second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress) is etched away in a wet etching manner ( Col. 25 lines 36 – 39 The support layer may be deposited, in some instances, using an etching process).
Claim 15: Renzas discloses a quantum device ( Col 17. lines 8 – 11 FIG. 3 presents a schematic diagram of an example method 300 for fabricating a quantum circuit on a substrate 302 having a superconducting via 304 and a first surface 306 that is fully uncovered) comprising a circuit component formed by multiple superconducting materials ( Fig. 1C #130 and #132 ), and the multiple superconducting materials are obtained by using a method for preparing multi-superconducting material layers ( Fig. 1C #130 and #132 ), the method comprising: depositing a first superconducting material layer ( Fig. 1C #130 ) on a substrate ( Fig. 1C #102 ), the first superconducting material layer ( Fig. 1C #130 ) being formed by covering a first superconducting material ( Col. 8 lines 62 – 66 the first layer 130 may be formed of niobium with compressive stress ) in a first target region range ( Fig. 1C right side of substrate ) with a first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) in the first target region range ( Fig. 1C right side of substrate ); depositing a second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress) on the substrate ( Fig. 1C #102 ) deposited with the first superconducting material layer ( Fig. 1C #130 ); covering the second superconducting material ( as discussed above ) with a second hard mask ( as discussed above ); and performing etching treatment ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) on the second hard mask ( as discussed above ) and the second superconducting material ( as discussed above ) to obtain a second superconducting material layer ( Fig. 1C #132 ) formed by covering the second superconducting material ( as discussed above ) in a second target region range ( Fig. 1 C right side of substrate area ) with the second hard mask ( as discussed above ) in the second target region range ( as discussed above ).
Renzas does not appear to disclose the first target region range and the second target region range are separated.
However, MacLean teaches the first target region range and the second target region range are separated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of MacLean with Renzas to implement the first target region range and the second target region range are separated because this approach allows independent selective deposition and patterning of different superconducting materials on the same substrate.
Claim 19: Renzas discloses a quantum chip ( Col. 16 lines 44 – 47 Such features may correspond to bond pads, electrical pads, or other structures that allow integration of the quantum circuit (and substrate 200) in a 3D package ), comprising a quantum device ( Col 17. lines 8 – 11 FIG. 3 presents a schematic diagram of an example method 300 for fabricating a quantum circuit on a substrate 302 having a superconducting via 304 and a first surface 306 that is fully uncovered ), wherein the quantum device comprising a circuit component formed by multiple superconducting materials ( Fig. 1C #130 and #132 ), and the multiple superconducting materials are obtained by using a method for preparing multi-superconducting material layers ( Fig. 1C #130 and #132 ), the method comprising: depositing a first superconducting material layer ( Fig. 1C #130 ) on a substrate ( Fig. 1C #102 ), the first superconducting material layer ( Fig. 1C #130 ) being formed by covering a first superconducting material ( Col. 8 lines 62 – 66 the first layer 130 may be formed of niobium with compressive stress ) in a first target region range ( Fig. 1C right side of substrate ) with a first hard mask ( Col. 8 lines 46 – 55 In some embodiments the superconducting materials and support materials may be patterned or otherwise processed in such a way as to reduce stress. In some embodiments, material deposition techniques may result in excess material on the backside of the wafer due to imperfect material transfer into the vias, leading to unnecessarily high overall wafer stress and increasing the challenge of subsequent backside patterning, if desired. Methods during deposition may include shadow masked deposition ) in the first target region range ( Fig. 1C right side of substrate ); depositing a second superconducting material ( Col. 8 lines 62 - 66 the second layer 132 formed of an alloy of molybdenum and rhenium with tensile stress) on the substrate ( Fig. 1C #102 ) deposited with the first superconducting material layer ( Fig. 1C #130 ); covering the second superconducting material ( as discussed above ) with a second hard mask ( as discussed above ); and performing etching treatment ( Col. 8 lines 55 – 59 Methods after deposition of some or all layers may optionally include, for instance, chemical mechanical polishing or a patterned etch to either thin down or remove excess material on the backside of the wafer ) on the second hard mask ( as discussed above ) and the second superconducting material ( as discussed above ) to obtain a second superconducting material layer ( Fig. 1C #132 ) formed by covering the second superconducting material ( as discussed above ) in a second target region range ( Fig. 1 C right side of substrate area ) with the second hard mask ( as discussed above ) in the second target region range ( as discussed above ).
Renzas does not appear to disclose the first target region range and the second target region range are separated.
However, Maclean teaches the first target region range and the second target region range are separated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of MacLean with Renzas to implement the first target region range and the second target region range are separated because this approach allows independent selective deposition and patterning of different superconducting materials on the same substrate.
Claim 14 is rejected under U.S.C. 103 as being unpatentable over Renzas et al.; US 11,276,727 B1; 06/2018 in view of MacLean et al.; US 2023/0187503 A1; 08/2021 as it relates to claim 11 above and further in view of Lee; US 2010/0105595 A1; 10/2008
Claim 14: Renzas and MacLean disclose the method according to claim 11 ( as discussed above ).
Neither Renzas nor MacLean appear to disclose an etching agent used by the wet etching manner is an SC-1 solution.
However, Lee teaches an etching agent used by the wet etching manner ( [0105] The surface treatment composition of the present invention is used for surface treatment operations including cleaning, etching, polishing, film-forming and the like, for substrates such as semiconductor, metal, glass, ceramics, plastic, magnetic material, superconductor and the like, the metal impurity contamination of which becomes troublesome ) manner is an SC-1 solution ( [0048] Sometimes the SC1 solution is also called the APM solution, which stands for Ammonia Hydrogen Peroxide Mixture. The SC1 solution is mainly used for removing particles and residual organic contamination ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Renzas and MacLean to implement an etching agent used by the wet etching manner is an SC-1 solution because this solution provides controlled surface cleaning and minimal surface damage.
Claims 16 and 20 are rejected under U.S.C. 103 as being unpatentable over Renzas et al.; US 11,276,727 B1; 06/2018 in view of MacLean et al.; US 2023/0187503 A1; 08/2021 as it relates to claim 15 above and further in view of Poccia et al.; US 12,593,618 B2; 06/2022
Claim 16: Renzas and MacLean disclose the quantum device according to claim 15 ( as discussed above).
Neither Renzas nor MacLean appear to disclose the quantum device is a Fluxonium quantum bit.
However, Poccia teaches the quantum device is a Fluxonium quantum bit ( Col. 4 lines 8 - 9 The qubit may be a fluxonium qubit, in particular π fluxonium qubit ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Poccia with Renzas and MacLean to implement the quantum device is a Fluxonium quantum bit because this material provides superior coherence and reduced noise.
Claim 20: Renzas and MacLean disclose the quantum chip according to claim 19 ( as discussed above).
Neither Renzas nor MacLean appear to disclose the quantum device is a Fluxonium quantum bit.
However, Poccia teaches the quantum device is a Fluxonium quantum bit ( Col. 4 lines 8 - 9 The qubit may be a fluxonium qubit, in particular π fluxonium qubit ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Poccia with Renzas and MacLean to implement the quantum device is a Fluxonium quantum bit because this material provides superior coherence and reduced noise.
Response to Amendment/Arguments
Applicant’s arguments, see page 10 of remarks, filed 07/08/26, with respect to Drawings have been fully considered and are persuasive. The objection of 04/08/26 has been withdrawn.
Applicant’s arguments, see pages 11-12, filed 07/08/26, with respect to the rejections of claims 1, 15, and 19 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of MacLean.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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