DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s amendment of claims 1, 4-6 and 9-10, and cancellation of claims 2-3, 7-8 and 11-39 in “Claims - 04/27/2026” is acknowledged. Claims 1, 6 is noted as independent claims.
This office action considers claims 1, 4-6 and 9-10 pending for further prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 100; Fig 9(a); [0019]) = (element 100; Figure No. 9(a); Paragraph No. [0019]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document..
Claims 1, 4-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over WU; Hsiao-Che et al. (US 20090023268 A1) hereinafter Wu’268; in view of Chua; Soo Jin et al. (US 20090001416 A1) hereinafter Chua; and Sakaguchi, Kiyofum et al. (US 20040082149 A1) hereinafter Sakaguchi..
Regarding claim 1. Wu’268 teaches an integrated circuit (IC; fig 1; [0029]) including (see the entire document, Figs 1-7 along with other relevant figures, specially Fig 7, and as cited below)
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Wu’268 Figure 7
one or more (depicted at least 2two in Fig 7) porous semiconductor isolation111’; Figs 6-7; [0036]) converted from a crystalline semiconductor material (An anodization process is performed to the isolation region 111 to convert the p-type bulk silicon of the isolation region 111 into porous silicon 111),
But, Wu’268 does not expressly disclose wherein the one or more porous semiconductor isolation structures (111’) include a protective cap of recrystallized semiconductor. The difference between and the claim is “a protective cap of recrystallized semiconductor”.
However, in the analogous art, Chua, ([0007]) citing Sakaguchi , discloses a porous semiconductor layer (100) on a semiconductor region of the semiconductor substrate (130); forming a non-porous semiconductor layer (110) on the porous semiconductor layer; forming a semiconductor element and/or semiconductor integrated circuit in the non-porous semiconductor layer. The porous semiconductor layer is a porous silicon layer formed by anodizing the surface of a single-crystal silicon wafer or an ion-implanted layer formed by implanting hydrogen ions, helium ions, or rare gas ions to a desired depth of a single-crystal silicon wafer. After annealing, a non-porous thin film such as a single-crystal Si, GaAs, InP, or GaN film is grown on the porous silicon layer (100) by CVD or the like. More particularly Sakaguchi teaches ([0037]) a non-porous thin film (110; Fig 1a) such as a single-crystal silicon film is grown on the porous silicon layer by CVD or the like, that is being used as protective film (0038) over porous silicon film (100). Chua further discloses [0033] The lateral size of the pores varies from 20 nm to 200 nm.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Chua/Sakaguchi’s teaching into Wu’268’s and thereafter, the combination discloses protective cap of recrystallized semiconductor, since this inclusion at least protect the underlying porous silicon layer.
Regarding claim 4, The combination of (Wu’268’s and Chua/Sakaguchi ) as applied to the integrated circuit of claims 1 , while further teaches,
wherein the one or more porous semiconductor isolation structures (111’) but does not expressly disclose “comprises microporous semiconductor”. It is noted in claim rejection 1 (above) that Chua discloses [0033] the lateral size of the pores varies from 20 nm to 200 nm
However, the Applicant has not presented persuasive evidence that microporous semiconductor is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness), since it clamed (in claims 5 and 10) mesoporous semiconductor . Also, the applicant has not shown that the claimed microporous semiconductor produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It is noted that instant specification defines in paragraph [0039] microporous π-Semi (pore diameters φ less than about 2 nm) or mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm),
Examiner like to note MPEP 2144.05.I, specifically, In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018), wherein the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 2nm" and the prior art range of "Chua 20 nm” were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality.).
Therefore, the microporous semiconductor of claimed is not patentable over prior art disclosed porous semiconductor of 20 nm.
Regarding claim 5. The combination of (Wu’268’s and Chua/Sakaguchi ) as applied to the integrated circuit of claim 1, further teaches, wherein the one or more porous semiconductor isolation structures (111’) comprises mesoporous semiconductor (obvious in view of Chua’s [0033] the lateral size of the pores varies from 20 nm to 200 nm and instant specification defines in paragraph [0039] mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm) semiconductor.
Regarding claim 6. Wu’268 teaches an integrated circuit (IC; fig 1; [0029]) including (see the entire document, Figs 1-7 along with other relevant figures, specially Fig 7, and as cited below)
at least one transistor structure ([0006]: Active areas (AA) are regions of a substrate on which the transistors are located ) surrounded by at least one of the one or more (depicted at least two in Fig 7) porous semiconductor isolation structures 111’; Figs 6-7; [0036]) converted from a crystalline semiconductor material (An anodization process is performed to the isolation region 111 to convert the p-type bulk silicon of the isolation region 111 into porous silicon 111), wherein the one or more porous semiconductor isolation structures include a protective cap of recrystallized semiconductor.
But, Wu’268 does not expressly disclose wherein the one or more porous semiconductor isolation structures (111’) include a protective cap of recrystallized semiconductor. The difference between and the claim is “a protective cap of recrystallized semiconductor”.
However, in the analogous art, Chua, ([0007]) citing Sakaguchi , discloses a porous semiconductor layer (100) on a semiconductor region of the semiconductor substrate (130); forming a non-porous semiconductor layer (110) on the porous semiconductor layer; forming a semiconductor element and/or semiconductor integrated circuit in the non-porous semiconductor layer. The porous semiconductor layer is a porous silicon layer formed by anodizing the surface of a single-crystal silicon wafer or an ion-implanted layer formed by implanting hydrogen ions, helium ions, or rare gas ions to a desired depth of a single-crystal silicon wafer. After annealing, a non-porous thin film such as a single-crystal Si, GaAs, InP, or GaN film is grown on the porous silicon layer (100) by CVD or the like. More particularly Sakaguchi teaches ([0037]) a non-porous thin film (110; Fig 1a) such as a single-crystal silicon film is grown on the porous silicon layer by CVD or the like, that is being used as protective film (0038) over porous silicon film (100). Chua further discloses [0033] The lateral size of the pores varies from 20 nm to 200 nm.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Chua/Sakaguchi’s teaching into Wu’268’s and thereafter, the combination discloses protective cap of recrystallized semiconductor, since this inclusion at least protect the underlying porous silicon layer.
Regarding claim , The combination of (Wu’268’s and Chua/Sakaguchi ) as applied to the integrated circuit of claims 6 , while further teaches,
wherein at least one of the one or more porous semiconductor isolation structures (111’) but does not expressly disclose “comprises microporous semiconductor”. It is noted in claim rejection 1 (above) that Chua discloses [0033] the lateral size of the pores varies from 20 nm to 200 nm
However, the Applicant has not presented persuasive evidence that microporous semiconductor is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness), since it clamed (in claims 5 and 10) mesoporous semiconductor . Also, the applicant has not shown that the claimed microporous semiconductor produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It is noted that instant specification defines in paragraph [0039] microporous π-Semi (pore diameters φ less than about 2 nm) or mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm),
Examiner like to note MPEP 2144.05.I, specifically, In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018), wherein the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 2nm" and the prior art range of "Chua 20 nm” were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality.).
Therefore, the microporous semiconductor of claimed is not patentable over prior art disclosed porous semiconductor of 20 nm.
Regarding claim 10. The combination of (Wu’268’s and Chua/Sakaguchi ) as applied to the integrated circuit of claim 6, further teaches,
wherein of the one or more porous semiconductor isolation structures (111’) comprises mesoporous semiconductor (obvious in view of Chua’s [0033] the lateral size of the pores varies from 20 nm to 200 nm and instant specification defines in paragraph [0039] mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm) semiconductor .
Response to Arguments
Applicant's arguments “Remarks - 04/27/2026- Applicant Arguments/Remarks Made in an Amendment, have been fully considered, but they are not persuasive because of the following:
Applicant’s amendment of claims 1, 4-6 and 9-10 changed the scope of the inventions significantly, and necessitated the shift in new grounds of rejection detailed in section 1, supra. The shift in grounds of rejection renders Applicant’s arguments moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached on M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
June 9, 2026
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