DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of group I, claims 1-10, in ”Response to Election / Restriction Filed - 12/04/2025”, is acknowledged along with cancellation of claims 11-17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 100; Fig 9(a); [0019]) = (element 100; Figure No. 9(a); Paragraph No. [0019]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 5-7 and 10 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Divakaruni; Ramachandra et al. (US 20090206442 A1) hereinafter Divakaruni
Regarding claim 1. Divakaruni teaches an integrated circuit (100; Fig 9(a)-9(b); 0019]) including (see the entire document, Figs 9(a)-9(b), 14 along with subject matter referenced in other figures, specifically, as cited below) .
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Divakaruni Figures 9(a) -9(b); and Figure 14
at least one porous semiconductor isolation structure (122 with opening 114 and filled area 108, Fig 9(a)-9B; [0019-0020]; opening 114 in between fill material 108 labeled as [0007] one or more STI regions (122) porous; see also claim 1: a plurality of vertically oriented nano-scale openings (114) in the trench fill material (108); and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions (122) in the substrate (100)).
Regarding claim 2. Divakaruni as applied to the integrated circuit of claim 1, further teaches, wherein the at least one porous semiconductor isolation structure (122) includes a protective cap (110; Fig 14).
Regarding claim 5. Divakaruni as applied to the integrated circuit of claim 1, further teaches, wherein the at least one porous semiconductor isolation structure (122) comprises mesoporous (because of opening of 10 nm to 40 nm [0018] and instant specification defines in paragraph [0039] mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm) semiconductor {114,108}.
Regarding claim 6. Divakaruni teaches an integrated circuit (100; Fig 9(a)-9(b); 0019]) including (see the entire document, Figs 9(a)-9(b), 14 along with subject matter referenced in other figures, specifically, as cited below) .
at least one transistor structure ( a gate structure 120; Fig 9a-9b; [0020]) surrounded by a porous semiconductor isolation structures (122 with opening 114 and filled area 108, Fig 9(a)-9B; [0019-0020]; opening 114 in between fill material 108 labeled as [0007] one or more STI regions (122) porous; see also claim 1: a plurality of vertically oriented nano-scale openings (114) in the trench fill material (108); and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions (122) in the substrate (100))..
Regarding claim 7. Divakaruni as applied to the integrated circuit of claim 6, further teaches, wherein the at least one porous semiconductor isolation structure (122) includes a protective cap (110; Fig 14).
Regarding claim 10. Divakaruni as applied to the integrated circuit of claim 6, further teaches, wherein the at least one porous semiconductor isolation structure (122) comprises mesoporous (because of opening of 10 nm to 40 nm [0018])and and instant specification defines in paragraph [0039] mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm) semiconductor {114,108}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Divakaruni; Ramachandra et al. (US 20090206442 A1) hereinafter Divakaruni.
Regarding claims 4, 9. Divakaruni as applied to the integrated circuit of claims 1 and/or 6, while further teaches, wherein the at least one porous semiconductor isolation structure (122) but does not expressly disclose “comprises microporous semiconductor” {114,108}.
However, the Applicant has not presented persuasive evidence that microporous semiconductor is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness), since it clamed (in claims 5 and 10) mesoporous semiconductor . Also, the applicant has not shown that the claimed microporous semiconductor produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It is noted that instant specification defines in paragraph [0039] microporous π-Semi (pore diameters φ less than about 2 nm) or mesoporous π-Semi (pore diameters φ between about 2 nm and 50 nm),
Examiner like to note MPEP 2144.05.I, specifically, In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018), wherein the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 2nm" and the prior art range of "6 nm” were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality.).
Therefore, the microporous semiconductor of claimed is not patentable over prior art disclosed porous semiconductor of 10 nm.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Divakaruni; Ramachandra et al. (US 20090206442 A1) hereinafter Divakaruni; in view of Kovacs; Terrence et al., (US 4444620 A) hereinafter Kovacs.
Regarding claims 3. 8 Divakaruni as applied to the integrated circuit of claims 1 and/or 6, while further teaches, wherein the at least one porous semiconductor isolation structure (122; Fig 14) includes a protective cap (110), but was silent on “of recrystallized semiconductor”.
However, in the analogous art, Kovacs teaches Growth Of Oriented Single Crystal Semiconductor On Insulator (title), wherein in (Column 3, Lines 8-20) highly perfect, capped, laterally recrystallized semiconductor material on buried insulator can be produced if the cap is appropriately patterned. It is thought to be of benefit also with other techniques for lateral recrystallization of capped semiconductor films on buried insulator, e.g., with the above-mentioned global melting technique. Furthermore, we believe that patterning can be advantageously used in semiconductor/insulator systems other than Si/SiO.sub.2, e.g., Ge, III-V or II-VI semiconductors such as GaAs, InP, and ZnS on oxides (including, where applicable, native oxide), nitrides, carbides, or borides.
Therefore, it would have been obvious to one of ordinary skill in the, before the effective filing date of the claimed invention, to adopt the teaching of Kovac’ capped recrystallized semiconductor material for Divakaruni’s porous semiconductor isolation structure (122) and teaches the claimed limitation, since, this inclusion of Semiconductor material on insulator recrystallized can advantageously be employed for device manufacture, e.g., manufacture of electronic devices such as MOSFET or bipolar transistors, optoelectronic devices, or integrated optics devices( Kovacs Column 7, Lines 55-61).
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
January 31, 2026