DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/02/2026 has been entered.
The Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/02/2026 have been fully considered but they are not persuasive.
(1) Applicant argues “Element 106 of Wu is a bottom semiconductor layer of the substrate 102, and not "a superstructure", as that term is used in the present application and as known and used by practitioners of ordinary skill in the art.” It interpreted that the applicant is suggesting the structure of the106 layer in the Wu reference does not qualify as a suffer structure because there is supposed to be distinct definition of superstructure well known in the art in which layer 106 does not match the requirements.
Examiner argues superstructure is a generic term with an indistinct definition coined by the applicant to name a layer in the semiconductor structure with no specific chemical composition uniqueness or structural assembly properties. The Wu 106 layer qualifies as a superstructure do to the layer being present in a semiconductor device and compatible with the semiconductor device functionality.
Applicant argues, the asserted superstructure of Wu, bottom semiconductor layer 106, is not "bonded to a surface of the handle wafer" - there is no handle wafer in FIG. 1 or FIG. 12 of Wu.
The Advisory Action argues that "(2) The handle wafer element is provided in the Gardener reference (FIG 1; 101; [0033])". However, there is no suggestion or teaching in Gardener or Wu as to how one might make use of a handle wafer in conjunction with Wu, whose stacked layers of FINFETs neither need nor appear to even be able to use a handle wafer in the manner claimed by Applicant.
Examiner argues the handle wafer 101 of Gardener is able to be bonded with the first superstructure of Wu 106. The first superstructure of the Gardner reference. The surface of the handle wafer can be placed beneath the superstructure of Wu 106.
(3) Applicant argues, the asserted superstructure of Wu, bottom semiconductor layer 106, does not include "a gate contact electrically connected to the gate layer" - gate contacts 1202, 1204 of Wu are not included as part of the bottom semiconductor layer 106.
a. The Advisory Action argues that "(3) "a gate contact electrically connected to the gate layer" was read as a separate element from the super structure."
Applicant fails to see how this argument supports the Examiner's position – claim 1, for example, requires "a first superstructure ..., the first superstructure including ... a gate contact electrically connected to the gate layer". A gate contact in Wu that is not part of the claimed superstructure does not meet this claim limitation.
Examiner argues the gate contacts 1202 and 1204 are included as part of the bottom semiconductor layer.
Claim was read as the first superstructure including a source contact electrically connected to the at least one source cap...(separately) and a gate contact electrically connected to the gate layer. The Claim was not interpreted, the first superstructure also including a source contact electrically connected to the at least one source cap and the superstructure also including a gate contact electrically connected to the gate layer.
The claim limitation is met when the first superstructure including a source contact electrically connected to the at least one source cap…is read separately from, and a gate contact electrically connected to the gate layer.
Applicant argues Elements 302 and 304 are not source contacts, but rather are fin structures that comprise the channels of the VTFETs.
The Advisory Action argues that "(4) Elements 302 and 304 are doped semiconductor material in contact with the source/drain layers making them source contacts."
Elements 302 and 304 of Wu are quite clearly transistor channels and not sources or source contacts in the sense known in the art (306 and 510 are the source/drain regions). Applicant has amended the prior language of independent claims 1 and 27 ("middle portion of the one or more nano-pillar structures") to clarify that the middle portion is not a source (or drain) contact, but instead a transistor channel:
"middle transistor channel portion of the one or more nano-pillar structures".
Accordingly, the combination of Wu and Gardner fails to teach or suggest all of the elements of claims 1, 4-8, and 25-32, and thus cannot obviate the invention as now claimed in such claims.
Examiner Argues, the fins structures have the material composition, position and performance of a source contact, making them source contacts.
Advisory action statement is correct.
Source/drain contacts can be represented as fin structures 302 and 304.
Wu discloses (Col 7 Ln 64-67 and Col 8 Ln 1) “This process forms a first doped fin region in a portion of the bottom fin 302, 304 laterally contacted by the first bottom source/ drain 306, 308. In some embodiments, the junctions may have a height of, for example, 4 nm to 10 nm Although other dimensions are applicable as well. ” The lower portions of the fin in contact with the source/drain are described as distinct areas with measurable dimensions on the bottom fin that are in contact with the source/drain layer and composed of material found in common source/drain contacts, making them source/drain contacts. The amendments to the prior language on Claim 1 and 27 do not overcome the rejection and are not related to the refences Wu 302 or 304. The middle transistor channel portion is referenced in Gardner 105. Also the middle transistor portion 105 is taught in Gardner because 105 is the middle of the vertical channel region 410 making it a transistor channel.
Gardner and Wu teach all the elements of Claim 1, 3-8, 25-32.
Applicant argues, In the final Office Action, dependent claim 3 was rejected under 35 U.S.C. 103 as being unpatentable over Gardner and Wu as applied to claims 1, 3-8 [sic, should be 4-8], and 25-32, and further in view of Figure 2 of the admitted prior art of Applicant's own disclosure in the instant application. Applicant respectfully traverses this rejection with respect to the claims as currently presented.
The deficiencies of Gardner and Wu are noted above. Fig. 2 of the present application is asserted as teaching "wherein the drain region is diffused across the second end of one or more nano-pillar structures", which fails to remedy the lack in the combination of Gardner and Wu of "a first superstructure adjacent to the first end of the one or more nano-pillar structures and bonded to a surface of the handle wafer, the first superstructure including a source contact electrically connected to the at least one source cap and a gate contact electrically connected to the gate layer".
Accordingly, the combination of Gardner, Wu, and Fig. 2 of the present application fails to teach or suggest the invention as presently claimed, and thus cannot obviate dependent claim 3.
Examiner argues Gardner and Wu combination reject claim 1 in which claim 3 is dependent on. The admitted prior art of the applicant teaches “wherein the drain region is diffused across the second end of one or more nano-pillar structures”.
Claim Objections
Claim 3, 4, 6, 7, and 8 are objected to because of the following informalities: Claiming
canceled claim 2. Appropriate correction is required. The dependent claims are dependent on claim
1. Change the claims to being dependent on claim 1 since claim 2 is canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8 and 25-32 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner(US20230207660A1) and Wu(US11069679B2).
Regarding Claim 1, A vertical nano-pillar field-effect transistor (FET), including:
(a) a handle wafer (101; Fig 1; ¶[0033]);
(b) an inverted nano-pillar FET including:
(1) one or more nano-pillar structures each having a first end (FIG 4; 305; ¶[0036]), a middle transistor channel portion (FIG 4; 105; ¶[0033]; middle portion of a vertical channel region 410 ¶[0036]), and a second end (FIG 4; 113; ¶[0033]);
(2) at least one source cap (FIG 6; 605; ¶[0037]), each source cap in electrical contact with the first end of an associated nano-pillar structure of the one or more nano-pillar structures (FIG 8; 814; ¶[0039]);
(3) a gate layer surrounding the middle transistor channel portion of the one or more nano-pillar structures (FIG 6; 603; ¶[0037]);
(4) a drain region in electrical contact with the second end of the one or more one nano- pillar structures (FIG 4; 111; ¶[0037]);
bonded to a surface of the handle wafer (101; Fig 1; ¶[0033])
Gardener does not teaches
(5) a first superstructure adjacent to the first end of the one or more nano-pillar structures and, the first superstructure including a source contact electrically connected to the at least one source cap and a gate contact electrically connected to the gate layer; and
(6) a second superstructure adjacent to the second end of the one or more nano-pillar structures, the second superstructure including a drain contact electrically connected to the drain region.
Wu teaches in FIG 1 and FIG 12
(5) a first superstructure (FIG 1 and FIG 12; 106, 1202, 1204, 302, 304, 412 and 414; Col 4 Ln 54-59; Col 6 Ln 22-25; Col 15 Ln 34-44) adjacent to the first end of the one or more nano-pillar structures, the first superstructure including a source contact (FIG 12; 302 and 304; Col 6 Ln 22-25) electrically connected to the at least one source cap and a gate contact electrically connected to the gate layer (FIG 12; 412 and 414; Col 15 Ln 34-44); and
(6) a second superstructure adjacent to the second end of the one or more nano-pillar structures (FIG 12; 908; Col 14 Ln 48-62), the second superstructure including a drain contact electrically connected to the drain region (FIG 12; 902 and 904; Col 14 Ln 13-17).
It would be obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the invention of Gardner, a semiconductor device with a handle wafer and inverted nano-pillars, with the pillars being comprised of a first end, middle transistor channel portion and a second end, a source cap, a gate layer, and a drain region and the invention of Wu, a semiconductor device comprising a first superstructure adjacent to the first end of the nano-pillar and second superstructure adjacent to the second end of the nano-pillars. This combination would produce a semiconductor device with a handle wafer and inverted nano-pillars, with the pillars being comprised of a first end, middle transistor channel portion and a second end, a source cap, a gate layer, and a drain region and a first superstructure adjacent to the first end of the nano-pillar and second superstructure adjacent to the second end of the nano-pillars. This structure have the superstructure features to perform electrical functions in a protected environment Wu(Column 14 Line 60-62).
Regarding Claim 4, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 1.
Gardner teaches in Fig 4, wherein the drain region is not diffused (Fig 4; 111; ¶ [0037]); a
diffusion process for metal in drain region is not mentioned) across the second end of the one or more
nano-pillar structures.
Regarding Claim 5, Gardner and Wu teach in the vertical nano-pillar field effect transistor
of Claim 4.
Gardner teaches in Fig 4 and Fig 8, including at least one body contact (Fig 8; 814; ¶ [0040])
connected to an undiffused region (Fig 4; 111; ¶ [0037]) near the drain-side end of at least one of the
one or more nano-pillars.
Regarding Claim 6, Gardner and Wu teach in the vertical nano-pillar field effect transistor
of Claim 1.
Gardner teaches in ¶ [0020], wherein the one or more nano-pillar structures include at least one nanowire structure (¶ [0020]; metal wiring layer contains nanowires).
Regarding Claim 7, Gardner and Wu teach in Fig 4 the vertical nano-pillar field effect
transistor of Claim 1.
Gardner teaches in ¶ [0031] and Fig 4, wherein the one or more nano-pillar structures include at least one nanosheet structure (¶ [0031]; stacks of nanosheets) (Fig 4; 410; ¶ [0036]; Nanosheet vertical
channels).
With respect to Claim 8, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 1.
Gardner teaches in Fig 6, wherein the one or more nano-pillar structures include at least two
nanosheet structures spanned by a common fin-like nanosheet (Fig 6; 501; ¶ [0037]).
Regarding Claim 25, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 1.
Gardner teaches in Fig 4, wherein the one or more nano-pillar structures comprised silicon (Fig
4; 105; ¶ [0033]).
With respect to Claim 26, Gardner and Wu teach in Fig 6 the vertical nano-pillar field effect
transistor of Claim 1.
Gardner teaches in Fig 6 including:
(a) a first dielectric layer formed around the one or more nano-pillars between the at least one
source cap and the gate layer; and (Fig 6; 601; ¶ [0036])
(b) a second dielectric layer formed around the one or more nano-pillars between the gate layer
and the drain region (Fig 6; 209; ¶ [0036).
Regarding Claim 27, Gardner teaches in Fig 1, Fig 4, Fig 6 and Fig 8, a vertical nano-pillar
field-effect transistor (FET), including:
(a) a handle wafer (101; Fig 1; ¶ [0033]); and
(b) an inverted nano-pillar FET (410; Fig 4; ¶ [0036]) including:
(1) one or more nano-pillar structures each having a first end (305; Fig 4; ¶ [0036]), a middle transistor channel portion (105; Fig 4; ¶ [0033]; middle portion of a vertical channel region 410 ¶[0036]), and a second end (113; Fig 4; ¶ [0033]);
(2) at least one source cap (605; Fig 6; ¶ [0037]), each source cap formed on and in electrical contact with the first end of an associated nano-pillar structure of the one or more nano-pillar structures (814; Fig 8; ¶ [0039]);
(3) a gate layer surrounding the middle transistor channel portion of the one or more nano-pillar structures (603; Fig 6; ¶ [0037]);
(4) at least one drain cap, each drain cap formed on and in electrical contact with the second end of an associated nano-pillar structure of the one or more nano-pillar structures (111; Fig 4; ¶ [0037]; diffusion process for metal in drain region is not mentioned);
bonded to a surface of the handle wafer (101; Fig 1; ¶ [0033])
Gardner does not teach
(5) A first superstructure adjacent to the first end of the one or more nano-pillar structures and, the first superstructure including a source contact electrically connected to the at least one source cap and a gate contact electrically connected to the gate layer; and
(6) A second superstructure adjacent to the second end of the one or more nano-pillar
structures, the second superstructure including a drain contact electrically connected to the drain region
Wu teaches in Fig 1 and 12
(5) A first superstructure (Fig 1 and Fig 12; 106, 1202, 1204, 302, 304, 412 and 414; ; Col 4 Ln 54-59; Col 6 Ln 22-25; Col 15 Ln 34-44) adjacent to the first end of the one or more nano-pillar structures and bonded to a surface of the handle wafer (¶ [25-34]), the first superstructure including a source contact (Fig 12; 302 and 304; Column 6 Line 22-25) electrically connected to the at least one source cap (Fig 12; 306 and 308; Column 6 Line 40-46) and a gate contact (Fig 12; 1202 and 1204; Column 15 Line 59-67) electrically connected to the gate layer (Fig 12; 412 and 414; Column 15 Line 34-44); and
(6) A second superstructure adjacent to the second end of the one or more nano-pillar structures (Fig 12; 908; Column 14 Lines 58-62), the second superstructure including a drain contact electrically connected to the drain region (Fig 12; 902 and 904; Column 14 Lines 13-17)
It would be obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the invention of Gardner, a semiconductor device with a handle wafer and inverted nano-pillars, with the pillars being comprised of a first end, middle transistor channel portion and a second end, a source cap, a gate layer, and a drain region and the invention of Wu, a semiconductor device comprising a first superstructure adjacent to the first end of the nano-pillar and second superstructure adjacent to the second end of the nano-pillars. This combination would produce a semiconductor device with a handle wafer and inverted nano-pillars, with the pillars being comprised of a first end, middle transistor channel portion and a second end, a source cap, a gate layer, and a drain region and a first superstructure adjacent to the first end of the nano-pillar and second superstructure adjacent to the second end of the nano-pillars. This structure have the superstructure features to perform electrical functions in a protected environment Wu(Column 14 Line 60-62).
Regarding Claim 28, Gardner and Wu teach in the vertical nano-pillar field effect transistor of Claim 27.
Gardner teaches in ¶ [0020], wherein the one or more nano-pillar structures include at least one nanowire structure (¶ [0020]; metal wiring layer contains nanowires).
Regarding Claim 29, Gardner and Wu teach in the vertical nano-pillar field effect transistor
of Claim 27.
Gardner teaches in ¶ [0029] wherein the one or more nano-pillar structures include at least one
nanosheet structure (¶ [0029] Ln 16-20).
Regarding Claim 30, Gardner and Wu teach in Fig 4 the vertical nano-pillar field effect
transistor of Claim 27.
Gardner teaches in Fig 4 and ¶ [0031], wherein the one or more nano-pillar structures include at
least two nanosheet structures spanned by a common fin-like nanosheet (¶ [0031]; stacks of
nanosheets) (410, Fig 4; ¶ [0036]; Nanosheet vertical channels).
Regarding Claim 31, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 27.
Gardner teaches in Fig 4, wherein the one or more nano-pillar structures comprised silicon (Fig
4; 105; ¶ [0033]).
Regarding Claim 32, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 27.
Gardner teaches in Fig 6 further including:
(a) a first dielectric layer formed around the one or more nano-pillars between the at least one source cap and the gate layer (Fig 6; 601; ¶ [0036]); and
(b) a second dielectric layer formed around the one or more nano-pillars between the gate layer and the at least one drain cap (Fig 6; 209; ¶ [0036]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner and Wu as applied
to claim 1, 3-8 and 25-32 above, and further in view of Figure 2 of the admitted prior art of the
applicant’s own disclosure in the instant application.
Regarding Claim 3, Gardner and Wu teach the vertical nano-pillar field effect transistor of
Claim 1.
Gardner does not teach wherein the drain region is not diffused across the second end of the
one or more nano-pillar structures.
Figure 2 of the admitted prior art of the applicant’s own disclosure in the instant application
teaches wherein the drain region is diffused across the second end of one or more nano-pillar structures
(Fig 2; 210; ¶ [0004]).
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the claimed invention to combine the invention from the prior art of Gardner, a method
to fabricate vertical nano-pillar field effect transistors with three portions, a gate-all-around
region and a source/drain contact at the end of each nano-pillar, the invention of Wu, a
semiconductor including two superstructures, and the invention from Figure 2 of the admitted
prior art disclosed in the instant application, a vertical transistor assembly with a diffused drain
region along the end of the nanopillar. The combination in inventions would produce multiple
embodiments of nano-pillar transistors that have a wider range of ion diffusion in the drain
regions to enable more diverse electronic applications.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
Zhu(US20230060149A1): This reference teaches a three dimensional semiconductor memory device with two structures bonded together
Futatsuki(US20220359706A1): This reference teaches a semiconductor device with pillars
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/B.Q.R./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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