DETAILED ACTION
This action is responsive to the amendment received on 05/24/2026 and the request for continued examination (RCE) received on 06/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/24/2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-2, 4-7 and 15) in the reply filed on 01/20/2026 is acknowledged. Claim(s) 8-14 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 08/01/2022.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-7, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0075730 A1; Lee et al.; 03/2020; (“Lee”).
Regarding Claim 1. Lee discloses A semiconductor structure (Figures 20 and 21, semiconductor structure where Figure 20 is a layout and Figure 21 are cross sectional views according to [0123]), comprising a substrate (#101, Figure 21, substrate) and word line structures (#130, Figure 21, gate structure including gate electrode #132 which may be a word line according to [0131]);
wherein an isolation structure (#110, Figure 21, cell device isolation layer) is formed in the substrate (Figure 21, #110 is formed in #101), and the isolation structure defines active areas arranged in staggered rows in the substrate (#104, Figure 21 right panel, [0069], “cell device isolation layer 110 may define the cell active region 104”, Figures 20 and 18 of the method of making show that the active regions (#104) are arranged in staggered rows);
wherein the isolation structure comprises a trench formed in the substrate (Figure 21, [0108], “first insulating layer 112 [of #110] may define a trench”), an isolation layer filled in the trench (#112 and #116, Figure 21, first and second insulating layers), and a shielding layer (#114, Figure 21, cell shielding layer) located in the isolation layer (Figure 21, #114 is located in the trench shaped structure of #112 and #116), and in a top view, the shielding layer comprises a plurality of individual patterns arranged in staggered rows (Figures 20 and 18 of the method show that the shielding layers (#114/#214) surround the active layers which are arranged in staggered rows as described above and each grouping of particles for #114 are individual patterns arranged in staggered rows); and
wherein the word line structures are located in the substrate (Figure 21, #130s are located in the substrate #101), pass through the isolation structure and the active area alternately (Figure 21, #130s pass through alternating active regions #104 and cell device isolation layers #110), and are located above the shielding layer (Figure 21, #130 is located above #114),
wherein the isolation layer comprises:
a first isolation dielectric layer (#112, Figure 21, first insulating layer) located at a bottom and sidewalls of the trench (Figure 21, #112 is located at a bottom and sidewalls of the trench in which #110 is formed); and
a second isolation dielectric layer (#116, Figure 21, second insulating layer) located on a surface of the first isolation dielectric layer and under the shielding layer (Figures 21, #116 is on a surface of #112 and extends partially underneath #114 to make contact with #112, see Figure 1B showing a zoomed in image of how the second insulating layer #26 extends under the shielding layer #24 to contact first insulating layer #22);
wherein the shielding layer is atop the second isolation dielectric layer (Figure 21, #114 is at least partially atop #116; [0130], “shielding layer 114 may include a plurality of particles spaced apart from each other and may not be in contact with the gate insulating film 131”, i.e. the use of the phrase “may not” is interpreted as envisioning an embodiment where there may be contact between particles of #114 and #131 such that those portions of #114 are atop #116 since there is no #116 between them and #131).
Regarding Claim 2. Lee discloses The semiconductor structure of claim 1, wherein a distance between the shielding layer and bottoms of the word line structures (Figure 21, [0130], “shielding layer 114 may include a plurality of particles spaced apart from each other and may not be in contact with the gate insulating film 131”, i.e. the use of the phrase “may not” is interpreted as envisioning an embodiment where there may be contact between particles of #114 and #131 such that the distance is zero therebetween; Examiner notes that the gate structure is formed by etching trenches into the structure where shielding layer particles have been formed to the top of the substrate (see Figure 13) such that the etch may expose at least one particle of #114 on which #131 is formed) is smaller than a distance between the shielding layer and a bottom of the isolation structure along a direction perpendicular to a plane on which the substrate is located (Figure 24, #114 is separated from a bottom of #110 by at least the thickness of #112 along a vertical direction perpendicular to the top of the substrate, i.e. a separation of zero through direct contact between #114 and #131 is smaller than the separation between #114 and the bottommost surface of #110).
Regarding Claim 5. Lee discloses The semiconductor structure of claim 1, wherein word line trenches are formed in the substrate (Figure 21, trenches passing through #101 in which #130s are located), and
a word line structure is located in each of the word line trenches (Figure 21, each of the trenches includes a #130 therein); and
wherein the word line structure (#130) comprises:
a gate dielectric layer (#131, Figure 21, gate insulating film) located at a bottom and sidewalls of a word line trench (Figure 21, #131 is located on a bottom and sidewalls of the trenches in which #130s are located); and
a word line conductive layer (#132, Figure 21, gate electrode which may be a word line according to [0131]) located on a surface of the gate dielectric layer (Figure 21, #132 is located on a surface of #131).
Regarding Claim 6. Lee discloses The semiconductor structure of claim 5, wherein an upper surface of the word line conductive layer is lower than a top surface of the word line trench (Figure 21 right pane, an upper surface of #132 is lower than a top surface of the trench in which #130s are located), and
the word line structure (#130) further comprises:
a filling dielectric layer (#133, Figure 21, gate capping film which may be an insulating/dielectric material according to [0132]) located on a surface of the word line conductive layer and filling the word line trench (Figure 21, #133 is located on an upper surface of #132 and at least partially fills the trenches in which #130s are located).
Regarding Claim 7. Lee discloses The semiconductor structure of claim 1, wherein each of the active areas (#104) further comprises:
a source (#104b, Figure 21, second impurity region which may be a source region according to [0133]), the source being located at one side of a corresponding one of the word line structures passing through a corresponding active area (Figure 21, [0133], #104b extends through an active region #104 at a side of one of the gate electrodes #132); and
a drain (#104a, Figure 21, first impurity region which may be a drain region according to [0133]), the drain being located at a side of the word line structure passing through the corresponding active area away from the source (Figure 21, [0133], #104a extends through the active region #104 at a side of the gate electrode #132 and is necessarily away from the source region to form a channel therebetween).
Regarding Claim 15. Lee discloses A memory structure, comprising the semiconductor structure of claim 1 (Figure 21, [0067], the region CELL shown in Figure 21 may be a cell array for a semiconductor memory device such as DRAM).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0075730 A1; Lee et al.; 03/2020; (“Lee”).
Regarding Claim 4. Lee discloses The semiconductor structure of claim 1.
Lee does not disclose, as part of the Figure 21 embodiment, that the isolation layer further comprises: a third isolation dielectric layer located in the trench and between the shielding layer and the word line structures.
However, Lee also teaches an alternative embodiment of the semiconductor device (Figures 4 and 5) wherein the isolation layer (#112, #116, and #118, Figures 4 and 5, first, second, and third insulating layers) further comprises a third isolation dielectric layer (#118, Figure 5, third insulating layer) located in the trench (Figure 5, #118 is in the isolation layer trench) and between the shielding layer and the word line structures (Figure 5 and 21, incorporation of #118 into Figure 21 would necessarily result in #118 being at least partially between the bottommost portions of #114 and the word line structures above).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the two embodiments disclosed adjacent to each other in the prior art reference, Lee, as doing so does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009). Incorporating the feature of a third isolation dielectric layer to the isolation layer from the embodiment of Figure 5 into the embodiment of Figure 21 would modify the insulative properties of the cell device isolation layer (see [0086]-[0088] of Lee) through modifying the horizontal width and the material properties therein.
Response to Arguments/Amendments
Applicant’s amendments to claim 1 and corresponding arguments, see pages 8-10 of the remarks, filed 03/18/2026, with respect to the 35 U.S.C. 102 rejection of claim 1, and all 35 U.S.C. 102 and 103 rejections of the dependent claims, have been fully considered but are not found persuasive. The 35 U.S.C. 102(a)(1) rejection of claim 1 is maintained.
Applicant argues that Lee does not disclose “the shielding layer is atop the second isolation dielectric layer” as recited in amended claim 1. In particular, applicant argues that the shielding layer of Lee (#114, Figure 21) includes a plurality of particles which are not atop the second insulating layer (#116, Figure 21). The examiner respectfully disagrees.
Examiner first notes that [0130] of Lee states “shielding layer 114 may include a plurality of particles spaced apart from each other and may not be in contact with the gate insulating film 131”, i.e. the use of the phrase “may not” is interpreted as envisioning an embodiment where there may be direct contact between topmost particles of #114 and #131 such that those portions of #114 have no portion of #116 above them. Under this interpretation, the topmost particles of #114 are necessarily atop #116 and read on the amended claim language. Examiner further notes that under a broader interpretation of the limitation, all of the particles of #114 which are along the sidewalls of #112 are at least partially atop #116 in that they all sit above some portion of #116 located beneath them. For these reasons it is the examiner’s interpretation the Lee does disclose all of the limitations of amended claim 1.
Claims 1, 2, 5-7, and 15 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0075730 A1; Lee et al.; 03/2020; (“Lee”).
Claim 4 stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0075730 A1; Lee et al.; 03/2020; (“Lee”).
Applicant’s request for rejoinder of method claims 8-14 based on the believed allowability product claim 1, see page 10 of the remarks, filed 03/18/2026, has been fully considered but is not found persuasive. Claim 1 stands rejected as described above. Claim(s) 8-14 stand withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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