DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, species I reading on Claims 1-11, according to applicant, without traverse is acknowledged. Claims 12-20 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by THEN et al. (IS 2020//0227544), (hereinafter, THEN).
RE Claim 1, THEN discloses GaN-based transistors with field plates and a method of making the same. THEN discloses in FIGS. 1-7 a semiconductor device comprising:
a semiconductor substrate 304 comprising an upper surface and a channel 302, referring to FIG. 3A;
one or more lower dielectric layers 380/322 disposed on the upper surface of the semiconductor substrate 304, wherein a source opening 372, a drain opening 374, a gate opening 343, and a field plate opening 342, referring to FIGS. 3I, 3K extend through the one or more lower dielectric layers to the semiconductor substrate, wherein the gate opening is between the source opening 372 and the drain opening 374, and the field plate opening 342 is between the gate opening 343 and the drain opening 374, referring to FIGS. 3G and 3J;
a conformal dielectric layer 366 “gate dielectric” disposed over the one or more lower dielectric layers 380/322 and into at least the gate opening 343 and the field plate opening 342, wherein the conformal dielectric layer 366 includes first portions formed on sidewalls of the gate opening 343, second portions formed on sidewalls of the field plate opening 342, and a third portion formed on the semiconductor substrate 304 at a bottom extent of the field plate opening 342, referring to FIGS. 3I, 3K;
gate spacers 340 disposed on the first portions of the conformal dielectric layer 366, referring to FIG. 3I;
a gate electrode 354 disposed in the gate opening 343 in contact “indirect contact” with the gate spacers 340 and the semiconductor substrate 304; and
a field plate 364 disposed in the field plate opening 342 in contact with the second and third portions of the conformal dielectric layer 366, referring to FIGS. 3I – 3K.
RE Claim 2, THEN discloses semiconductor device, wherein:
the conformal dielectric layer 366 further includes a fourth portion formed on the semiconductor substrate 304 at a bottom extent of the gate opening 343, referring to FIGS. 3I, 3K, wherein the gate electrode 354 extends through an opening in the fourth portion to contact “indirect contact” the semiconductor substrate 304, and wherein the gate spacers 340 are formed on both the first and fourth portions “sidewalls” of the conformal dielectric layer 366, referring to FIGS. 3I, 3K.
RE Claim 3, THEN discloses semiconductor device, wherein:
the conformal dielectric layer 366 “gate dielectric” is formed from a dielectric material “high-k dielectric” selected from aluminum oxide and aluminum nitride [0041].
RE Claim 5, THEN discloses semiconductor device, wherein:
the gate spacers 340 are formed from silicon nitride [0035].
RE Claim 6, THEN discloses semiconductor device, wherein:
the gate electrode 354 has a T-shaped cross-section, referring to FIS. 3I-3J with a stem 352 that extends through the one or more lower dielectric layers 380/322 to contact the semiconductor substrate 304 “indirect contact through the polarization layer 306”, and first and second protruding regions, “portion 354”, that extend over the gate spacers 340 and the one or more lower dielectric layers 380/322, referring to FIGS. 3I, 3K.
RE Claim 7, THEN discloses semiconductor device, wherein:
the field plate 364 is recessed below an upper surface of the one or more lower dielectric layers 380/322.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over THEN et al. (IS 2020//0227544), (hereinafter, THEN).
RE Claim 4, THEN does not disclose semiconductor device, wherein:
the conformal dielectric layer has a thickness in a range of 50 angstroms to 200 angstroms.
However, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the instant application use the claimed thickness for the conformal dielectric 366, absent unexpected results, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Allowable Subject Matter
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Hill (US 2023/0361183) discloses a transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel opening, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel opening, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel opening prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel opening, the length of the gate structure can be advantageously decreased.
Bothe et al. (US 2022/0376085) disclose a method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.
PARK (US 2017/0104097) discloses a high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898