Prosecution Insights
Last updated: April 19, 2026
Application No. 18/451,819

SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

Non-Final OA §103§112
Filed
Aug 17, 2023
Examiner
WARD, ERIC A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
91%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
561 granted / 726 resolved
+9.3% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
29 currently pending
Career history
755
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 726 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 6,8,10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/12/2025. Applicant asserts on page 1 that claim 1 is generic to the claimed species, but this is incorrect since claim 1 recites for example “wherein the first semiconductor element is of a rectangle having a long side extending in the first direction in the top view, the second semiconductor element is of a quadrangle having a side extending in the first direction in the top view, the first semiconductor element and the second semiconductor element are disposed so that the long side of the first semiconductor element faces the side of the second semiconductor element” which is shown in Species A FIG. 9 chips 7 and 9 facing each other but not in Species B FIG. 11 with stacked chips 9 and 7. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-5,7,9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 1 lines 25-26 recites “the second gate pad is disposed on the second semiconductor element on the other side in the first direction.” but the reference to “the other side” lacks proper antecedent basis within the claim since claim 1 lacks an introduction of “an other side”. Although Applicant may have intended for “the other side” to be interpreted relative to “on one side” of claim 1 line 23, claims are interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) consistent with the specification and therefore for purposes of examination “the other side” is interpreted as referring more generally to one of the other sides other than the side facing the first semiconductor element. Claims 2-5,7,9 are rejected insofar as they depend upon and include all of the limitations including the indefinite language of claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-4,7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2022/0224327 A1 to Ikeda, “Ikeda”, in view of U.S. Patent Application Publication Number 2019/0123034 A1 to Nakamura, “Nakamura”. Regarding claim 1 insofar as definite, Ikeda discloses a semiconductor device (FIG. 2), comprising: a first semiconductor element (11, ¶ [0027]-[0029]) and a second semiconductor element (12, ¶ [0027]-[0029]) that are connected in parallel with each other (FIG. 1, ¶ [0023]); a control integrated circuit (15, ¶ [0031],[0032]) controlling driving of the first semiconductor element (11) and the second semiconductor element (12); a first gate pad (G11) disposed on the first semiconductor element (11) and receiving a signal (through 102 connected to G11) for controlling the driving of the first semiconductor element (11); a second gate pad (G12) disposed on the second semiconductor element (12) and receiving a signal (through 102 connected to G12) for controlling the driving of the second semiconductor element (12); a first wire (102 connected to G11) connecting the control integrated circuit to the first gate pad (G11); and a second wire (102 connected to G12) connecting the control integrated circuit to the second gate pad (G12), wherein the first semiconductor element (11) is of a rectangle having a long side extending in a first direction in the top view (e.g. up-down axis in FIG. 2), the second semiconductor element (12) is of a quadrangle (smaller rectangle) having a side extending in the first direction in the top view, the first semiconductor element (11) and the second semiconductor element (12) are disposed so that the long side of the first semiconductor element (11) faces the side of the second semiconductor element (12), and the control integrated circuit (which must be to the left based on the direction of 102), the first semiconductor element (11), and the second semiconductor element (12) are disposed in this order in a direction orthogonal to the first direction (left-right axis, since 102 is connected to the control integrated circuit), the first gate pad (G11) is disposed on the first semiconductor element (11) on one side (upwards the top) in the first direction, wherein the second gate pad (G12) is disposed on the second semiconductor element (12) on the “other side” (wherein the other side is interpreted as the side facing upwards in FIG. 2) in the first direction. PNG media_image1.png 681 849 media_image1.png Greyscale Ikeda fails to clearly teach in sufficient detail the control integrated circuit (15) being of a rectangle having a long side extending in a first direction in a top view. Nakamura teaches (FIG. 4) wherein a control integrated circuit (3N) is a rectangle having a long side extending in a first direction (left-right axis, since long sides of 1UN and 1VN face each other along the left-right axis) in a top view. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda with a rectangular control integrated circuit along a first direction as exemplified by Nakamura in order to achieve miniaturization of the power module (Nakamura ¶ [0065]). Regarding claim 2, Ikeda in view of Nakamura yields the semiconductor device according to claim 1, and although Ikeda discloses wherein an angle between the first wire (102 connected to G11) and the first direction ranges from 80° to 100° (90 degrees as pictured), Ikeda fails to clearly teach in sufficient detail for anticipation wherein the angle between the second wire (102 connected to G12) and the first direction is also 80° to 100°. However, Nakamura shows (FIG. 4) wherein the angles of the wires connected from the semiconductor elements (a 10 on each of 1UN, 1VN, 1WN) and the control integrated circuit (3N) are within the claimed range (approximately 90 degrees) with the analogous first direction. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda in view of Nakamura with the angles within the claimed ranges as suggested by Ikeda and Nakamura since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the angles determine the package dimensions and therefore miniaturization of the package making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Regarding claim 3, although Ikeda in view of Nakamura yields the semiconductor device according to claim 1, Ikeda fails to clearly teach wherein the first semiconductor element (11) contains SiC. However, Ikeda teaches wherein the second semiconductor element (12) contains SiC (¶ [0029]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda in view of Nakamura by swapping the position of the first and second semiconductor elements since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include: (A) Combining prior art elements according to known methods to yield predictable results; (B) Simple substitution of one known element for another to obtain predictable results; (C) Use of known technique to improve similar devices (methods, or products) in the same way; (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results; (E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success; (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art; (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention, wherein in the instant case it would have been obvious to apply simple substitution of swapping the first and second semiconductor elements with the predictable and desired result of forming a functioning switching apparatus. Regarding claim 4, although Ikeda in view of Nakamura yields the semiconductor device according to claim 1, and Ikeda fails to clearly teach wherein the first semiconductor element (11) is smaller in chip area than the second semiconductor element (12) in the top view. Rather, Ikeda further teaches wherein the second semiconductor element (12) is smaller in chip area (as pictured) than the first semiconductor element (11) in the top view. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda in view of Nakamura by swapping the position of the first and second semiconductor elements since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include: (A) Combining prior art elements according to known methods to yield predictable results; (B) Simple substitution of one known element for another to obtain predictable results; (C) Use of known technique to improve similar devices (methods, or products) in the same way; (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results; (E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success; (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art; (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention, wherein in the instant case it would have been obvious to apply simple substitution of swapping the first and second semiconductor elements with the predictable and desired result of forming a functioning switching apparatus. Regarding claim 7, although Ikeda in view of Nakamura yields the semiconductor device according to claim 1, Ikeda fails to clearly teach wherein the first semiconductor element is a metal-oxide-semiconductor field-effect transistor, and the second semiconductor element is an insulated gate bipolar transistor. Rather, Ikeda further teaches wherein the second semiconductor element (12) is a metal-oxide-semiconductor field-effect transistor (¶ [0027]-[0029]), and the first semiconductor element (11) is an insulated gate bipolar transistor (¶ [0024]-[0026]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda in view of Nakamura by swapping the position of the first and second semiconductor elements since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include: (A) Combining prior art elements according to known methods to yield predictable results; (B) Simple substitution of one known element for another to obtain predictable results; (C) Use of known technique to improve similar devices (methods, or products) in the same way; (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results; (E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success; (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art; (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention, wherein in the instant case it would have been obvious to apply simple substitution of swapping the first and second semiconductor elements with the predictable and desired result of forming a functioning switching apparatus. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2022/0224327 A1 to Ikeda, “Ikeda”, in view of U.S. Patent Application Publication Number 2019/0123034 A1 to Nakamura, “Nakamura”, as applied to claim 1 above, and further in view of U.S. Patent Application Publication Number 2019/0198431 A1 to Zhang et al., “Zhang”. Regarding claim 9, Ikeda in view of Nakamura yields a power conversion device (switching apparatus in FIG. 1 as described by Ikeda, Nakamura power module (title)), comprising: a main conversion circuit (Ikeda FIG. 1) including the semiconductor device according to claim 1, the main conversion circuit converting an input power to output a resulting power; a control circuit (Ikeda’s 15) outputting, to the main conversion circuit, a control signal for controlling the main conversion circuit. Ikeda fails to clearly teach a radiating fin radiating outside heat generated by driving of the semiconductor device. Zhang teaches (e.g. FIG. 8) a radiating fin (16, ¶ [0022]) radiating (to the) outside heat generated by driving of semiconductor devices. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ikeda in view of Nakamura with a heat radiating fin as taught by Zhang in order to enhance the mechanical reliability of the power device (Zhang ¶ [0022],[0023]). Allowable Subject Matter Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Aug 17, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
91%
With Interview (+13.7%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 726 resolved cases by this examiner. Grant probability derived from career allow rate.

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