DETAILED ACTION
This Office action responds to Applicant’s election filed on 12/04/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The Applicant’s response on 12/04/2025 in reply to the restriction mailed on 10/27/2025 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Election/Restriction
The Applicant’s response on 12/04/2025 in reply to the restriction/election requirements mailed on 10/27/2025 has been entered. Applicant’s election of Invention I (claims 1-14, drawn to a semiconductor package structure), is acknowledged. Election was made without traverse in the reply filed on 12/04/2025.
Applicant’s election without traverse of Species 1 corresponding to fig. 1, drawn to claims 1-14, is acknowledged. Examiner disagrees. Claim 3 is related to Species 3 corresponding to fig. 3 (with one first chip stack structure connected to one second base and one second chip stack structure connected to another second base). Thus, claim 3 (and its depended claims 4-5) are withdrawn from consideration being related to a non-elected species.
Claims 3-5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claims 15-20 are withdrawn being related to a non-elected invention.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the filling layer located between the first semiconductor chip 20 and the first base 10 (see fig. 1 from the instant application) recited in claim 13 must be shown the drawings or the feature(s) canceled from the claim(s).
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu (US 2021/0143129) in view of Tain (US 2009/0294947).
Regarding claim 1, Okutsu shows (see, e.g., Okutsu: fig. 8) most aspects of the instant invention including a semiconductor package structure 1/20, comprising:
A first base 70
A first semiconductor chip 10 connected to the first base 70 (see, e.g., Okutsu: par. [0034], with the element of memory substrate 10 as a silicon substrate with circuits formed thereof)
A second semiconductor chip stack structure 20 (see, e.g., Okutsu: par. [0035]) located on the first semiconductor chip 10
The second semiconductor chip stack structure 20 comprising a plurality of second semiconductor chips 21 stacked in sequence in a first direction D (see, e.g., Okutsu: fig. 8, with stacking direction D)
The first direction D is a direction parallel to a plane of the first base 70
However, Okutsu fails (see, e.g., Okutsu: fig. 8) to show that the second semiconductor chip stack structure 20 being provided with a plurality of first leads on one of the second semiconductor chips 21 located at outermost of the second semiconductor chip stack structure 20 in the first direction. Tain, in a similar device to Okutsu, shows (see, e.g., Tain: fig. 5) that the second semiconductor chip stack structure 104/104/104 being provided with a plurality of first leads 122 on one of the second semiconductor chips 104 located at outermost of the second semiconductor chip stack structure 104/104/104 in the first direction (parallel to the element 133) (see, e.g., Tain: par. [0040]). Chen also shows (see, e.g., Tain: fig. 5) that the plurality of leads 122 are connected the outmost semiconductor chip 104 to the external connecting circuit 114 in order to form by design a plurality of signal vias electrically connected to the connecting circuits (see, e.g., Tain: par. [0040] and abstract).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a plurality of leads of Tain on one of the second semiconductor chips located at outermost of the second semiconductor chip stack structure in the device of Okutsu, in order to form by design a plurality of signal vias electrically connected to the external connecting circuits.
Okutsu in view of Tain shows (see, e.g., Tain: fig. 5):
At least one second base 102 (see, e.g., Tain: fig. 5, with stacks of elements 102)
Signal lines 116 (see, e.g., Tain: fig. 5, with stacks of elements 116) in the at least one second base 102 being connected to the plurality of the first leads 122
The at least one second base 102 being connected to the first base 133 in a direction perpendicular to the plane of the first base 133
Regarding claim 6, Okutsu in view of Tain shows (see, e.g., Okutsu: fig. 8) that the first semiconductor chip 10 and the second semiconductor chip stack structure 20 communicate by wireless (see, e.g., Okutsu: par. [0034] and par. [0035] – [0036], where elements 11 (from element 10) and 121 (from element 20), respectively, are non-contact communication circuits).
Regarding claim 13, Okutsu in view of Tain shows (see, e.g., Tain: fig. 5) shows a filling layer at least one of located between the second semiconductor chip stack structure and at he at least one second base, or located between the first semiconductor chip and the first base (see, e.g., Tain: annotated fig. 5).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Okutsu in view of Tain in further view of Nakano (US 10217726).
Regarding claim 2, Okutsu in view of Tain shows (see, e.g., Okutsu: fig. 8) most aspects of the invention (paragraphs 11-14) including a first semiconductor chip 10 and a plurality of the second semiconductor chips 21. Okutsu in view of Tain shows (see, e.g., Okutsu: fig. 8) that the plurality of the second semiconductor chips 21 comprises a Dynamic Random Access Memory (DRAM) chip (see, e.g., Okutsu: par. [0032]).
However, Okutsu in view of Tain fails (see, e.g., Okutsu: fig. 8) to show that the first semiconductor chip comprises a logic chip. Nakano, in a similar device to Okutsu in view of Tain, shows (see, e.g., Nakano: fig. 1A) a semiconductor chip 110 is a substrate that includes a logic chip (see, e.g., Nakano: col.2/II.47-59). Nakano also shows (see, e.g., Nakano: fig. 1A) that the logic chip 110 exchange power and data signals with the DRAM chips 120a/120b (see, e.g., Nakano: col.4/II.43-46), and the logic chip can be a controller (see, e.g., Nakano: col.2/II.63-65) that can improve latency by processing information closer to the DRAM chips.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a logic chip of Nakano as first semiconductor chip in the device of Okutsu in view of Tain, in order to improve latency by processing information closer to the DRAM chips.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu in view of Tain in further view of Yu (US 11152344).
Regarding claim 7, Okutsu in view of Tain shows (see, e.g., Okutsu: fig. 8) most aspects of the invention (paragraphs 11-14) including a first base 70, and a semiconductor chip 10. Okutsu in view of Tain also shows (see, e.g., Tain: fig. 5) an one second base 102 (see, e.g., Tain: fig. 5, with stacks of elements 102).
However, Okutsu in view of Tain fails (see, e.g., Okutsu: fig. 8) to show that a groove is provided in the first base 10. Yu, in a similar device to Okutsu in view of Tain, shows (see, e.g., Yu: fig. 10) a groove in the base 128. Yu also shows (see, e.g., Yu: fig. 10) that the groove is to accommodate a logic chip 102 and to facilitate various interconnect/fan-out structures in package structure 106 that electrically connect the semiconductor chips to a package substrate (see, e.g., Yu: col.5/II.24-29).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a groove in the base of Yu in the device of Okutsu in view of Tain, in order to accommodate a logic chip and to facilitate various interconnect/fan-out structures in package structure that electrically connect the semiconductor chips to a package substrate.
Okutsu in view of Tain in view of Yu shows (see, e.g., Yu: fig. 10) that:
The first semiconductor chip 102 is located in the groove
The first semiconductor chip 102 is connected to the first base 128 via first conductive bumps 106
The at least one second base (see, e.g., Yu: fig. 10, second base is the part of the element 302 on top of the bumps 310) is connected to the first base 128 via second conductive bumps 310
Regarding claim 8, Okutsu in view of Tain shows (see, e.g., Okutsu: fig. 8) most aspects of the invention (paragraphs 11-14) including a first base 70, and a semiconductor chip 10. Okutsu in view of Tain also shows (see, e.g., Tain: fig. 5) one second base 102 (see, e.g., Tain: fig. 5, with stacks of elements 102).
However, Okutsu in view of Tain fails (see, e.g., Okutsu: fig. 8) to show at least one second base is connected to the first base via second conductive bumps. Okutsu in view of Tain shows (see, e.g., Tain: fig. 5) that one second base 102 is directly connected to the first base 133. Yu, in a similar device to Okutsu in view of Tain, shows (see, e.g., Yu: fig. 10, the second base is the part of the element 302 on top of the bumps 310) that a second base that is connected to the first base 128 vias conductive bumps 310.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the direct connection of the second base to the first base of Yu or the bump connection of the second base to the first base of Okutsu in view of Tain because these were recognized in the semiconductor art for their use as elelctrical connections in semiconductor device packages, as taught by Yu and Okutsu in view of Tain, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Okutsu in view of Tain in view of Yu shows (see, e.g., Yu: fig. 10) that:
The first semiconductor chip 102 is located in the first base 128
The first semiconductor chip 102 is connected to the first base 128 via first conductive bumps 106
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okutsu in view of Tain in further view of Hong (US 2022/0406755).
Regarding claim 11, Okutsu in view of Tain shows (see, e.g., Tain: fig. 5) most aspects of the invention (paragraphs 11-14) including signal lines 122. Okutsu in view of Tain shows (see, e.g., Tain: fig. 5) that each of the plurality of the first leads 122 includes a first sub-lead and a second sub-lead.
However, Okutsu in view of Tain fails (see, e.g., Tain: fig. 5) to show that each of the signal lines comprises a ground line and a power line. Hong, in a similar device to Okutsu in view of Tain, shows (see, e.g., Hong: fig. 1) that the signal lines 114 (from the PR region that is equivalent to the second base from the instant application) comprises a ground line and a power line (see, e.g., Hong: par. [0029]). Hong also shows (see, e.g., Hong: fig. 1) that the first power/ground vias 114 are electrically connected to a power or ground circuit of the first die 100 (see, e.g., Hong: par. [0031]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a ground line and a power line of Hong in the device of Okutsu in view of Tain, in order to electrically connect to a power or ground circuit of the semiconductor dies.
Okutsu in view of Tain in view of Hong shows (see, e.g., Tain: fig. 5, and see, e.g., Hong: fig. 1) that the ground line is electrically connected to the first sub-lead, and the power line is electrically connected to the second sub-lead.
Allowable Subject Matter
Claims 9-10, 12, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814