Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of claims 1-9 in the reply filed on 03/05/2026 is acknowledged. The traversal is on the ground(s) that it should be no undue burden on the Examiner to consider all claims in the single application. This is not found persuasive because applicant did not present an argument addressing and error in the restriction. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (2015/0155876, hereinafter Jayasena) in view of Mohammed et al. (US 2018/0331037, hereinafter Mohammed). With respect to claim 1 , Jayasena discloses a semiconductor device (Fig. 9) , comprising: a base (Para 0033 – bulk silicon) ; and a plurality of semiconductor die sets located on a surface of the base (Para 0033-0034 ) and stacked in sequence along a first direction (Para 0017-0018; 0032; and 0035; die-stacked memory device - Fig. 2 ) , the plurality of semiconductor die sets being respectively connected to different ranks (Para 0025; number of ranks , the die-stacked memory device may implement four ranks, each rank implemented at a corresponding quadrant of each of the memory dies) , and the plurality of semiconductor die sets being all electrically connected to the base (Para 0034) , and the first direction being a thickness direction of the base (Para 0033 -0034 ) ; wherein each of the plurality of semiconductor die sets comprises a first die and a second die vertically interconnected (Para 0032 – vertical interconnect), and the first die and the second die are connected to a same rank (Para 0025). Jayasena does not explicitly disclose that the vertical interconnect can be a face-to-face bond ing of the first and the second die . In an analogous art, Mohammed discloses that the vertical interconnect can be a a face-to-face bond ing of the first and the second die (Para 0119 – first and second die s connected face to face in vertical interconnect). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena’s device by having Mohammad’s disclosure in order to increase interconnection density, low power consumption with reduced package size. Claims 2-3 , and 5 -6 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena / Mohammed in view of Pagaila et al. (US 2012/0181673, hereinafter Pagaila ). With respect to claim 2 , Jayasena/Mohammed discloses t he semiconductor device of claim 1 . Jayasena/ Mohammed does not explicitly disclose wherein, the semiconductor device further comprises a first connection pad located on a first surface of the second die away from the base along the first direction, the second die comprises a conductive pillar, wherein the first connection pad is electrically connected to the conductive pillar, and the conductive pillar penetrates through the second die. In an analogous art, Pagaila discloses wherein, the semiconductor device further comprises a first connection pad (254 of Fig. 14) located on a first surface of the second die (220) away from the base along the first direction (Fig. 14), the second die comprises a conductive pillar (250), wherein the first connection pad is electrically connected to the conductive pillar (Fig. 14 -Para 0069 ), and the conductive pillar penetrates through the second die (250 penetrates through 220). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad’s device by having Pagaila’s disclosure in order to connect different layers of the stack of a semiconductor device. With respect to claim 3 , Jayasena/Mohammed discloses the semiconductor device of claim 2 . Jayasena/Mohammed does not explicitly disclose wherein the first die comprises a plurality of first bond pads arranged at intervals, and the plurality of first bond pads are located on a third surface of the first die away from the base along the first direction, the second die further comprises a plurality of second bond pads arranged at intervals, the plurality of second bond pads are located on a second surface of the second die close to the base along the first direction; and a projection area of each of the plurality of first bond pads coincides with a projection area of a corresponding one of the plurality of second bond pads along the first direction, and each of the plurality of first bond pads is electrically connected to the corresponding one of the plurality of second bond pads. In an analogous art, Pagaila discloses wherein the first die (106 of Fig. 3c) comprises a plurality of first bond pads arranged at intervals (pads are arranged at intervals on the top of 106) , and the plurality of first bond pads are located on a third surface of the first die away from the base along the first direction (pads are arranged on the top of 106 which is away from the base 52 ) , the second die further comprises a plurality of second bond pads arranged at intervals (pads on the lower side of 58) , the plurality of second bond pads are located on a second surface of the second die close to the base along the first direction (lower side of 58 is closer to the base 52) ; and a projection area of each of the plurality of first bond pads coincides with a projection area of a corresponding one of the plurality of second bond pads along the first direction (Fig. 3c) , and each of the plurality of first bond pads is electrically connected to the corresponding one of the plurality of second bond pads (Para 0044-0045) . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad’s device by having Pagaila’s disclosure in order to connect different layers of the stack of a semiconductor device. With respect to claim 5 , Jayasena/Mohammed discloses the semiconductor device of claim 2. Jayasena/ Mohammed does not explicitly disclose a second connection pad located on the surface of the base; wherein each of the plurality of semiconductor die sets is electrically connected to the base through the first connection pad and the second connection pad. In an analogous art, Pagaila discloses a second connection pad located on the surface of the base (Fig. 3c – pads located on 52); wherein each of the plurality of semiconductor die sets is electrically connected to the base through the first connection pad and the second connection pad (Fig. 3c). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad’s device by having Pagaila’s disclosure in order to connect different layers of the stack of a semiconductor device. With respect to claim 6 , Jayasena/Mohammed/ Pagaila discloses the semiconductor device of claim 5. Jayasena/Mohammed does not explicitly disclose wherein each of the connection structures is configured to connect the first connection pad and the second connection pad. In an analogous art, Pagaila discloses wherein each of the connection structures is configured to connect the first connection pad and the second connection pad (Fig. 3c). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad’s device by having Pagaila’s disclosure in order to connect different layers of the stack of a semiconductor device. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jayasena/Mohammed/ Pagaila and further in view of Kim (US 2019/0244945, hereinafter Kim). With respect to claim 4 , Jayasena/Mohammed/ Pagaila discloses the semiconductor device of claim 3. Jayasena/Mohammed does not explicitly disclose wherein the second die further comprises a re-distributed layer located on the second surface, and configured to connect the second bond pad with the conductive pillar. In an analogous art, Pagaila discloses wherein the second die further comprises an active layer (108 of Fig. 3c) located on the second surface (108 is located on the bottom side of 58) , and configured to connect the second bond pad with the conductive pillar (108 connects the bond pads on the bottom side of 58 with conductive pillars 110) . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena /Mohammad’s device by having Pagaila’s disclosure in order to connect different layers of the stack of a semiconductor device. Jayasena/Mohammed/ Pagaila does not explicitly disclose that a re-distribution layer is provided on the active layer. In an analogous art, Kim discloses that a re-distribution layer is provided on the active layer (Para 0026 & 0033; 0048; 0064). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad / Pagaila ’s device by having Kim ’s disclosure in order to electrically connect different components of multiple layers of a semiconductor device . Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena/Mohammed/ Pagaila in view of Lee et al. (US 2009/0134528, hereinafter Lee). With respect to claim 7 , Jayasena/Mohammed/ Pagaila discloses the semiconductor device of claim 6. Jayasena/Mohammed/ Pagaila does not explicitly disclose an insulating layer located between the plurality of semiconductor die sets and the base, and a dielectric layer located between two adjacent ones of the plurality of semiconductor die sets. In an analogous art, Lee discloses an insulating layer (240/204 of Fig. 3B) located between the plurality of semiconductor die sets and the base (Fig. 3B), and a dielectric layer (206) located between two adjacent ones of the plurality of semiconductor die sets. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad/ Pagaila’s device by having Lee’s disclosure in order to avoid short circuiting between different components of a semiconductor device. With respect to claim 8 , Jayasena/Mohammed/ Pagaila /Lee discloses the semiconductor device of claim 7. Jayasena does not explicitly disclose a plurality of semiconductor die sets arranged in sequence along a second direction, the second direction being any direction in a plane on which the base is located. In an analogous art, Mohammed discloses a plurality of semiconductor die sets arranged in sequence along a second direction, the second direction being any direction in a plane on which the base is located (Fig. 11-14 – die sets arranged in vertical direction). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena’s device by having Mohammed’s disclosure in order to avoid short circuiting between different components of a semiconductor device. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jayasena/Mohammed/ Pagaila /Lee in view of Kim. With respect to claim 9 , Jayasena/Mohammed/ Pagaila /Lee discloses the semiconductor device of claim 8. Jayasena does not explicitly disclose a plastic packaging layer covering at least the plurality of semiconductor die sets and the base; wherein the base further comprises connection solder balls, the connection solder balls and the second connection pads are respectively located on two surfaces of the base along the first direction. In an analogous art, Pagaila discloses a plastic packaging layer covering at least the plurality of semiconductor die sets and the base (Para 0051; and 0158). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammad’s device by having Pagaila’s disclosure in order to protect components of a semiconductor device. Jayasena/Mohammed/ Pagaila /Lee does not explicitly disclose wherein the base further comprises connection solder balls, the connection solder balls and the second connection pads are respectively located on two surfaces of the base along the first direction. In an analogous art, Kim discloses wherein the base further comprises connection solder balls (Fig. 2 – solder balls on the lower surface of 100) , the connection solder balls and the second connection pads are respectively located on two surfaces of the base along the first direction (Fig. 2 – connection pads on the top of 100 ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jayasena/Mohammed/ Pagaila /Lee ’s device by having Kim’s disclosure in order to connect with external components . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov . Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899