Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8-10, 16-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Junker et al. (US 2011/0210401).
Regarding claim 1, Junker discloses an integrated circuit comprising:
a first transistor (207) including an active region (regions 213 and region 203 between adjacent regions 213) [Fig. 15];
a first stressor (215) of a first stressor type located directly over the active region;
a second stressor (219 or 231) of a second stressor type opposite the first stressor type located directly over the active region (213), wherein the first stressor and the second stressor each includes a portion that directly overlaps each other [Fig. 15].
Regarding claim 2, Junker discloses wherein the first stressor (215) and the second stressor (219) each include a portion that directly overlaps each other directly over the active region (213) [Fig. 15].
Regarding claim 3, Junker discloses wherein the first stressor and the second stressor each include a portion that directly overlaps each other directly over a current terminal region (213) of the first transistor [Fig. 15].
Regarding claim 5, Junker discloses a third stressor (233,235 or 237) of the second stressor type (219) located directly over the active region (213), wherein the first stressor (215) and the third stressor (233,235 or 237) each include a portion that directly overlaps each other [Fig. 15].
Regarding claim 6, Junker discloses wherein the first stressor (215) includes a portion that does not directly overlap the third stressor (233,235 or 237) [Fig. 15].
Regarding claim 8, Junker discloses wherein the first stressor (215) includes a portion that does not directly overlap with a portion of the second stressor (231) [Fig. 15].
Regarding claim 9, Junker discloses wherein the first stressor (215) is located directly over the entire active area, wherein the second stressor (219) is not located directly over the entire active area (regions 213 and region 203 between adjacent regions 213 corresponding to transistor 207) [Fig. 15].
Regarding claim 10, Junker discloses wherein the first stressor (215) is located directly over the second stressor (219) [Fig. 15].
Regarding claim 16, Junker discloses wherein the first stressor and the second stressor each include silicon nitride [paragraph 0024, 0027, and 0057].
Regarding claim 17, Junker discloses wherein the first transistor (207) includes a gate structure (209) , wherein the first stressor (215) is located directly over the gate structure and the second stressor (219) is not located directly over the gate structure [Fig. 15].
Regarding claim 19, Junker discloses wherein the first stressor serves as an etch stop layer for forming a terminal contact of the first transistor [paragraphs 0002 and 0005].
Regarding claim 20, Junker discloses an integrated circuit comprising:
a first field-effect transistor (FET) (207) including an active region [Fig. 15];
a first stressor (215) of a first stressor type located directly over the active region [Fig. 15];
a second stressor (219) of a second stressor type opposite the first stressor type located directly over the active region, wherein the first stressor and the second stressor each include a portion that directly overlaps each other over the active region (213) of the FET (207), wherein the first stressor (215) includes a portion that does not directly overlap with a portion of the second stressor (219) [Fig. 15].
Claims 1, 4 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 8748248).
Regarding claim 1, Wank discloses an integrated circuit comprising:
a first transistor (13/33) including an active region (regions 14/34 and region 10/30 between adjacent regions 14/34) [Figs. 1 and 4];
a first stressor (15/35) of a first stressor type located directly over the active region [Figs. 1 and 4];
a second stressor (16/36) of a second stressor type opposite the first stressor type located directly over the active region, wherein the first stressor and the second stressor each includes a portion that directly overlaps each other [Figs. 1 and 4].
Regarding claim 4, Wank discloses wherein the first stressor and the second stressor each include a portion that directly overlaps each other directly over a channel region of the first transistor (13/33) [Figs. 1 and 4].
Regarding claim 15, The court has held that a preamble is not limiting “where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention” Catalina Marketing International Inc. v. Coolsavings.com Inc., 62 USPQ2d 1781 (CA FC 2002) citing Rowe v. Dror, 112 F.3d 473, 478, 42 USPQ2d 1550, 1553 (Fed. Cir. 1997).
Allowable Subject Matter
Claims 7, 11-14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815