Prosecution Insights
Last updated: May 29, 2026
Application No. 18/451,879

INTEGRATED CIRCUIT WITH OVERLAPPING STRESSORS

Non-Final OA §102
Filed
Aug 18, 2023
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nxp Usa Inc.
OA Round
2 (Non-Final)
87%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
806 granted / 929 resolved
+18.8% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
955
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The indicated allowability of claim 18 is withdrawn in view of further considerations of the references to Junker et al. and Wang et al. Rejections based on the cited references follow. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 8, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Junker et al. (US 2011/0210401). Regarding claim 1, Junker discloses an integrated circuit comprising: a first transistor (205) including an active region (regions 213 and region 203 between adjacent regions 213) [Fig. 15]; a first stressor (219) of a first stressor type located directly over the active region [Fig. 15]; a second stressor (215) of a second stressor type opposite the first stressor type located directly over the active region (213), wherein the first stressor and the second stressor each includes a portion that directly overlaps each other [Fig. 15]. wherein the first stressor (219) is made of a first material and the second stressor (215) is made of a second material (different material) that is etch selectable from the first material (219) [Figs. 15 and 7-9, and paragraphs 0024, 0034 and 0039]. Regarding claim 2, Junker discloses wherein the first stressor (219) and the second stressor (215) each include a portion that directly overlaps each other directly over the active region (213) [Fig. 15]. Regarding claim 3, Junker discloses wherein the first stressor and the second stressor each include a portion that directly overlaps each other directly over a current terminal region (213) of the first transistor [Fig. 15]. Regarding claim 8, Junker discloses wherein the first stressor (219) includes a portion (e.g. portion located above sidewalls 211 and silicide layer 213) that does not directly overlap with a portion of the second stressor (215) [Fig. 15]. Regarding claim 15, the court has held that a preamble is not limiting “where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention” Catalina Marketing International Inc. v. Coolsavings.com Inc., 62 USPQ2d 1781 (CA FC 2002) citing Rowe v. Dror, 112 F.3d 473, 478, 42 USPQ2d 1550, 1553 (Fed. Cir. 1997). Regarding claim 16, Junker discloses wherein the first stressor and the second stressor each include silicon nitride [paragraph 0024, 0027, and 0055-0057]. Regarding claim 17, Junker discloses wherein the first transistor (205) includes a gate structure (209) , wherein the first stressor (219) is located directly over the gate structure and the second stressor (215) is not located directly over the gate structure [Fig. 15]. Regarding claim 19, Junker discloses wherein the first stressor serves as an etch stop layer for forming a terminal contact of the first transistor [paragraphs 0002 and 0005]. Claims 1, 4 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 8748248). Regarding claim 1, Wang discloses an integrated circuit comprising: a first transistor (13/33) including an active region (regions 14/34 and region 10/30 between adjacent regions 14/34) [Figs. 1 and 4]; a first stressor (15/17, 35/37) of a first stressor type located directly over the active region [Figs. 1 and 4]; a second stressor (16,36) of a second stressor type opposite the first stressor type located directly over the active region, wherein the first stressor and the second stressor each includes a portion that directly overlaps each other [Figs. 1 and 4]; wherein the first stressor (15/17,35/37) is made of a first material and the second stressor (16/36) is made of a second material that is etch selectable from the first material [col. 4, lines 46-64 and col. 5, lines 8-15]. Regarding claim 4, Wang discloses wherein the first stressor and the second stressor each include a portion that directly overlaps each other directly over a channel region of the first transistor (13/33) [Figs. 1 and 4]. Regarding claim 15, The court has held that a preamble is not limiting “where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention” Catalina Marketing International Inc. v. Coolsavings.com Inc., 62 USPQ2d 1781 (CA FC 2002) citing Rowe v. Dror, 112 F.3d 473, 478, 42 USPQ2d 1550, 1553 (Fed. Cir. 1997). Allowable Subject Matter Claims 7, 11-14, 18 and 20 are allowed. Claims 5-6 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim 18 have been considered but are moot. In the instant case, Junker teaches that “the first and second stressor materials may be…different” [paragraph 0024], and that the second stressor (215) is removed with a suitable etching step [paragraphs 0039. Also, see Figures 7-8 and paragraph 0034]. Hence, Junker does teach the limitation “wherein the first stressor is made of a first material and the second stressor is made of a second material that is etch selectable from the first material.” In addition, Wang teaches a first stressor stack comprising a liner (35) and a hard mask (37), and a second stressor (36) [Fig. 4]; wherein the material of the hard mask (37) of the first stressor stack is different from the material of the second stressor (36) [col. 5, lines 8-15], and the second stressor is further etched relative to the first stressor stack [col. 4, lines 56-61]. Also, Wang teaches that the first and second liners (35) and (36) are not limited to the same material [col. 4, lines 10-15]. Hence, Wang does teach the limitation “wherein the first stressor is made of a first material and the second stressor is made of a second material that is etch selectable from the first material.” As such, the rejections are considered to be proper. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Aug 18, 2023
Application Filed
Jan 21, 2026
Non-Final Rejection mailed — §102
Apr 13, 2026
Response Filed
Apr 27, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.5%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allowance rate.

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