DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 5/22/2008 "Reply" elects with traverse species B and identifies as reading on claims 1-3, 5-12, and 14-20.
In the restriction requirement Examiner has set forth why the restriction requirement is proper. Applicant has not provided a basis for why the restriction is improper. Accordingly, the restriction requirement is maintained and Examiner has withdrawn claims 4 and 13 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “…a joint of the first isolation layer and the third isolation layer being located on a side of the second isolation layer facing the substrate” of claims 5 and 14 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 10-12, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US Pub. No. 2023/0413518).
Regarding claim 1, in FIG. 4, Kim discloses a semiconductor structure, comprising a substrate (LS, paragraph [0046]) and a plurality of Word Lines (WLs) (WLE21, WLE22), the plurality of WLs extend in a first direction (D3), and are arranged on the substrate at intervals in a second direction (D1); for every two adjacent WLs, a WL isolation structure (IL and BR, paragraphs [0056] and [0059]) is arranged therebetween, the WL isolation structure comprising at least a first isolation layer (a bottommost BR) and a second isolation layer (IL adjacent to said bottommost BR) stacked in the second direction and made of different materials (IL is SiO, paragraph [0078]; BR is SiN, paragraph [0059]), and the first direction and the second direction intersecting with each other.
Regarding claim 2, in FIG. 4, Kim discloses that the WL isolation structure comprises the first isolation layer (a bottommost BR), the second isolation layer (IL adjacent to said bottommost BR) and a third isolation layer (a next BR adjacent to IL) sequentially stacked in the second direction, and the first isolation layer being made of the same material as the third isolation layer (both are a BR same material).
Regarding claim 3, in FIG. 4, Kim discloses that a material of one of the first isolation layer (BR is SiN, paragraph [0059]) and the second isolation layer comprises a nitride, and a material of the other of the first isolation layer and the second isolation layer comprises an oxide (IL is SiO, paragraph [0078]).
Regarding claim 5, in FIG. 4, Kim discloses in a cross section of the WL isolation structure in the second direction, the first isolation layer and the third isolation layer are connected to each other and form a U-shape structure (see leftmost portion of BR surrounding IL in FIG. 4), a joint (or an arbitrary portion; consistent with FIGs. 1-2 of the present application which appear to show 310 and 303 as continuous) of the first isolation layer and the third isolation layer being located on a side of the second isolation layer facing the substrate.
Regarding claim 10, in FIG. 4, Kim discloses a method for manufacturing a semiconductor structure, comprising: providing a substrate (LS, paragraph [0046]); and forming a plurality of Word Lines (WLs) (WLE21, WLE22) and WL isolation structures (IL and BR, paragraphs [0056] and [0059]), with the plurality of WLs extending in a first direction (D3) and being arranged on the substrate at intervals in a second direction (D1), wherein for every two adjacent WLs, a respective one of the WL isolation structures is arranged therebetween, each of the WL isolation structures at least partially comprising a first isolation layer (a bottommost BR) and a second isolation layer (IL adjacent to said BR) stacked in the second direction and made of different materials (IL is SiO, paragraph [0078]; BR is SiN, paragraph [0059]), first direction and the second direction intersecting with each other.
Regarding claim 11, in FIG. 4, Kim discloses that the WL isolation structure comprises the first isolation layer (a bottommost BR), the second isolation layer (IL adjacent to said bottommost BR) and a third isolation layer (a next BR adjacent to IL) sequentially stacked in the second direction, and the first isolation layer being made of the same material as the third isolation layer (both are a BR same material).
Regarding claim 12, in FIG. 4, Kim discloses that a material of one of the first isolation layer (BR is SiN, paragraph [0059]) and the second isolation layer comprises a nitride, and a material of the other of the first isolation layer and the second isolation layer comprises an oxide (IL is SiO, paragraph [0078]).
Regarding claim 14, in FIG. 4, Kim discloses in a cross section of the WL isolation structure in the second direction, the first isolation layer and the third isolation layer are connected to each other and form a U-shape structure (see leftmost portion of BR surrounding IL in FIG. 4), a joint (or an arbitrary portion; consistent with FIGs. 1-2 of the present application which appear to show 310 and 303 as continuous) of the first isolation layer and the third isolation layer being located on a side of the second isolation layer facing the substrate.
Allowable Subject Matter
Claims 6-9 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 6-9, in FIG. 2, Kim discloses a plurality of Bit Lines (BLs) (BL, paragraph [0021]) arranged on the substrate. However, the prior art failed to disclose or reasonably suggest the claimed semiconductor structure particularly characterized by the plurality of bit lines being located on a side of the WLs facing the substrate, the plurality of BLs extend along the second direction, and are arranged at intervals in the first direction, for every two adjacent BLs, a BL isolation structure is arranged therebetween.
Regarding claims 15-20, the prior art failed to disclose or reasonably suggest the claimed method for manufacturing a semiconductor structure particularly characterized by the providing the substrate comprising: forming a plurality of WL grooves and a plurality of Bit Line (BL) grooves located in the semiconductor layer, with a portion of the semiconductor layer located between the WL grooves and the BL grooves forming semiconductor columns, and a portion of the semiconductor layer located at bottom of the semiconductor columns forming the substrate; wherein the plurality of WL grooves extend in the first direction and are arranged the at intervals in the second direction, and the plurality of BL grooves extend in the second direction and are arranged at intervals in the first direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891