DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, Figs. 2A & 7, Claims 1-10 read on Fig. 2A and Claims 18-19 read on Fig. 7. New Claims 20-27 read on Figs. 2A or 7, and Claims 11-17 have been canceled, in the reply filed on 01/16/2026 is acknowledged.
It is note that the limitations as cited in claims 7 & 8 are not read on the selected Fig. 2A or Fig. 7, thus Claims 7 & 8 are withdrawn as well.
Priority
Foreign priority is not claim for the instant examining application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2023 and 09/14/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 1 (disclosed in background) should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-10, 20 & 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSIEH et al., (US 20120032743 A1), hereinafter Hsieh.
Regarding claim 1, Hsieh discloses in Fig. 7A a low noise amplifier (LNA) comprising:
a first transistor (transistor 712) and a second transistor (transistor 710) arranged in a series configuration, and
a tunable inductor (inductor 728 being connected to transistor 724 which act as a switch, hence inductor and transistor can be viewed as tunable inductor) coupling a gate terminal of the second transistor( gate terminal transistor 710) to ground;
wherein: the LNA is configured to receive an input signal (RFin signal at terminal 716) at an input terminal (terminal 716) coupled to the first transistor (transistor 712), and to generate an amplified signal (RFout) at an output terminal (terminal 722) coupled to the second transistor; and
the tunable inductor is configured such that a gate-source voltage of the second transistor (transistor 710) generated in presence (when switch 724 is closed) of the tunable inductor is larger than a gate-source voltage of the second transistor generated in absence (when the switch 724 open) of the tunable inductor.
Regarding claim 2, Hsieh discloses the LNA of claim 1, wherein the tunable inductor (inductor and switch 724 which control by signal at terminal Vsw1) is further configured to resonate out parasitics present at a source terminal of the second transistor (source terminal of transistor 710).
Regarding claim 4, Hsieh discloses the LNA of claim 1, further including a degenerative inductor (inductor 714) coupling a source terminal of the first transistor (transistor 712) to ground.
Regarding claim 9, Hsieh discloses the LNA of claim 1, further including an output matching circuit (output matching network 708) coupled to a drain terminal of the second transistor (transistor 710) and to the output terminal (terminal 722).
Regarding claim 10, Hsieh discloses the LNA of claim 1, wherein a resonance frequency of a combination of the tunable inductor and a gate-source capacitance of the second transistor is less than an operating frequency of the LNA ([0060], frequency may be 60 GHz much larger frequency than the tunable inductor and gate-source capacitance of the second transistor combined due to tunable inductance of the tunable inductor).
Regarding claim 20, Hsieh discloses the LNA of claim 1, wherein the tunable inductor is selectively switchable via a fourth switch (Fig. 7A, switch 724).
Regarding claim 27, Hsieh discloses the LNA of claim 1, wherein an out-of-phase voltage is generated at the gate terminal of the second transistor (transistor 710) if an operating frequency is less than a set resonant frequency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 5, 18-19 & 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Ayranci et al., (US 20220393650 A1, of record), hereinafter Ayranci.
Regarding claim 3, Hsieh discloses all the limitations as applied in claim 1 and further comprising an input matching circuit (matching network 706) except for inclusive of a series and a shunt inductor.
Ayranci discloses in Fig. 3B an amplifier circuit comprising an input matching circuit 306’ which includes an inductor LSH being connected between RFin terminal, inductor LSER and ground.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to replace generic input matching circuit of Hsieh with the specific input matching as taught by Ayranci. Such a modification would have imparted the advantageous benefit of reducing noise figure [0050] and increasing power transfer and performance ([0053]).
Regarding claim 5, Hsieh discloses all the limitations as applied in claim 4 except for wherein the degenerative inductor is adjustable and/or selectively switchable.
Ayranci discloses in Fig. 3B further discloses degeneration circuit 308′ which includes inductor LDEG’ in parallel with switch SWBP.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the degenerative inductor as taught by Hsieh to include the switch as taught by Ayranci. Such a modification would have imparted the advantageous benefit of noise reduction and increasing bandwidth and performance, see paragraph [0055].
Regarding claim 18, Hsieh discloses in Fig. 7A a low noise amplifier (LNA) comprising:
a first transistor (transistor 712) and transistor 710 are arranged in series configuration and one tunable inductor (inductor 728 being connected to transistor 724 which act as a switch, hence inductor and transistor can be viewed as tunable inductor) coupling gate terminal of corresponding transistor 710 to ground.
Hsieh does not teach two or more additional transistors, the first transistor and the two or more additional transistors being arranged in a series configuration.
Ayranci discloses in Fig. 3B the amplification core 302 which includes transistors MCS & MCG and additional more transistors in the FET stack 304, and wherein the amplification core 302 may have multiple FETs in a cascode configuration for the benefit of higher gain can be achieved [0039].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the cascode gain stage 702 as taught by Hsieh to include two or more additional transistor as taught by Ayranci. Such a modification would have imparted the advantageous benefit of higher gain can be achieved [0039].
As a consequence of the combination, two or more additional transistors (multiple series transistors as shown in fig. 3B of Ayranci) , the first transistor (Fig. 7A of Hsieh, 714) and the two or more additional transistors being arranged in a series configuration, and one or more tunable inductors (inductor 728 being connected to transistor 724 which act as a switch, hence inductor and transistor can be viewed as tunable inductor) coupling gate terminals of corresponding additional transistors of the two or more additional transistors to ground;
wherein:
the LNA is configured to receive an input signal (RFin) at an input terminal (716) coupled to the first transistor (712), and to generate an amplified signal at an output terminal (terminal 722) coupled to an additional transistor; of the two or more additional transistors; and the one or more tunable inductors are configured such that gate-source voltages of corresponding additional transistors of the two or more additional transistors generated in presence (Fig. 7A of Hsieh, switch 724 turn on or close) of the one or more tunable inductors are larger than gate-source voltages of said corresponding additional transistors of the two or more additional transistors generated in absence (switch 724 open) of the one or more tunable inductors.
Regarding claim 19, Hsieh discloses the LNA of claim 18, wherein at least one tunable inductor (inductor 728 connected to switch 724) of the one or more tunable inductors is selectively switchable (switch 724 for selecting close or open).
Regarding claim 21, Hsieh discloses all the limitations as applied in claim 4 except for wherein the degenerative inductor is selectively switchable via a fifth switch to adapt the LNA for different gain-bandwidth combinations.
Ayranci discloses in Fig. 3B further discloses degeneration circuit 308′ which includes inductor LDEG’ in parallel with switch SWBP (e.g., a fifth switch).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the degenerative inductor as taught by Hsieh to include the switch as taught by Ayranci. Such a modification would have imparted the advantageous benefit of noise reduction and increasing bandwidth and performance, see paragraph [0055].
Regarding claim 22, Hsieh discloses the LNA of claim 18, wherein the one or more tunable inductors (Fig. 7A of Hsieh, inductor 728 and switch 724) are capable of implemented only in correspondence with a top-most transistor that is located closest to the output terminal of the LNA.
Claims 6 & 25 rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Cho et al., (US 6882226 B2), hereinafter Cho.
Regarding claims 6 & 25, Hsieh discloses all the limitations as applied in claim 1, except for further including a feedback element coupling a drain terminal of the second transistor to a gate terminal of the first transistor.
Cho discloses in Fig. 6 an amplifier circuit comprising transistors MN61 and MN63 and wherein a feedback circuit includes capacitor C33 , inductor L31 and resistor R34 being connected between gate terminal of transistor MN61 and drain terminal of transistor MN63.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the circuit of Hsieh to include the feedback circuit as taught by Cho. Such a modification would have imparted the advantageous benefits of improving matching in a broad band and flat again in high frequency band (Col. 6, lines 27-32).
As a consequence of the combination, the feedback resistor (Fig. 6 of Cho: resistor R34) is capable of implemented to increase operational bandwidth and mitigate gain roll-off at higher frequencies.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Tong et al., (US 11652450 B2), hereinafter Tong.
Regarding claim 24, Hsieh discloses all the limitations as applied in claim 1 except for wherein the first and second transistors are fabricated using a Silicon- on-Insulator (SOI) or Silicon-on-Sapphire (SOS) based process to enable high-frequency operation exceeding 300 GHz.
Tong discloses an amplifier circuit comprising cascode circuit 202 having transistors M1 and M2 being connected in series and wherein cascode transistors can be fabricated using an SOI or SOS based process (Col. 12, lines 25-35).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to fabricate the first and second transistors of Hsieh using a Silicon- on-Insulator (SOI) or Silicon-on-Sapphire (SOS) based process to enable high-frequency operation exceeding 300 GHz in order to provide the benefits of low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz), Col. 12, lines 25-35).
Allowable Subject Matter
Claims 23 & 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 23 is allowable since the closest prior art (i.e. Hsieh) does not disclose configured to operate within a 5G FR3 frequency band, wherein the operating frequency is tuned between a wideband of 10-12.7 GHz and a narrowband of 10-10.5 GHz.
Claim 26 is allowable since the closest prior art (i.e. Hsieh) does not disclose
further comprising a switching network comprising at least three switches configured to selectively switch various circuit elements to toggle the LNA between a low gain mode and a high gain mode.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843