DETAILED ACTION
This action is responsive to the Request for Continuing Examination filed January 15, 2026. No claims have been amended. Claims 10 and 18 have been cancelled. Therefore, upon entry, claims 1-9, 11-17, and 19-20 are currently pending. Claims 1, 15, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/4/25 (as incorporated as the “submission for the RCE filed 1/15/26) has been entered.
Drawings
The amendments to the drawings for Figs. 3, 4A, and 4E are acknowledged and accepted. The objection to the drawings has been withdrawn.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 11-17, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1, 15, and 19, the term “desired amount” is a relative term which renders the claim indefinite. The term “desired amount” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Because of this indefiniteness, the limitation of the nature and magnitude of the claimed “variation from the baseline erase pulse parameter” is not clear.
For purposes of compact prosecution (see MPEP 2173.06), the term “desired amount of variation” will be interpreted to mean “an arbitrary value of pulse amplitude difference from the baseline initial erase voltage”.
Dependent claims 2-9, 11-14, 16-17, and 20 inherit the deficiency from their respective base claims and are therefore similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 9786378 – of Record) in view of Takizawa et al. (US 20170278581; “Takizawa”) as supported by Murugan et al. ("Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead"; “Murugan” – of Record)
Regarding independent claim 1, notwithstanding the indefiniteness rejection of claim 1 above, Zhang discloses an apparatus comprising:
a block of memory cells (Fig. 1A:126 array of memory cells);
and a control circuit coupled to the block of memory cells, the control circuit configured to perform an erase operation on the block of memory cells by (Fig. 1A:110 control circuitry):
receiving a desired amount of variation from a baseline erase pulse parameter (Fig. 14A:1402 and 1403. See also col. 19, ln. 12-14; "a baseline pulse width w1 and a baseline initial erase voltage Ver_init are used", in other words, the term Ver_init is analogous to the baseline pulse parameter in the instant application. And further see col. 19, ln. 20-22; "Erase voltages 1401, 1402 and 1403 are applied in the erase loops 1, 2 and 3, respectively", where 1402 and 1403 are the variation from the baseline erase pulse parameter 1401);
generating a first erase pulse comprising the desired amount of variation from the baseline erase pulse parameter (Fig. 15A where it illustrates a first pulse with a voltage of Ver_init_low which is lower than the baseline erase pulse parameter Ver_init. It is noted however that while Zhang's variation in this particular embodiment is similar to the embodiment in the instant application which this claim appears to be directed to (Fig. 12B), the specific electrical characteristics nor the magnitude of that variation is claimed and therefore this limitation has no patentable weight as that variation could be interpreted to be within the intrinsic noise level on the signal);
applying the first erase pulse to the block of memory cells, wherein the desired amount of variation from the baseline erase pulse parameter is selected so that the first erase pulse does not erase the block of memory cells (col. 20, ln. 14-21; “FIG. 15A depicts a plot of example erase voltages applied to a source line for a close block, where a baseline pulse width w1 and a low initial erase voltage Ver_init_low is used to provide a shallower erase. Compared to FIG. 14A, the initial erase voltage is lower. A result of this is that four erase loops are used instead of three to complete the erase operation. It is noted that the first erase pulse necessarily does not erase the block of memory cells because four erase loops are required to complete the erase operation),
and to reduce erase-induced damage to the block of memory cells (col. 11, ln. 34-36; "Additional components of memory device 100 include media management layer 238, which performs wear leveling of memory cells of non-volatile memory die 108." It is well understood in the art that "wear leveling" is a technique for minimizing damage done by P/E cycling (of which erase-induced damage is a component) as illustrated by Murugan (pg. 1, col. 2; “Wear out of blocks: Frequent block erase operations reduce the lifetime of flash memory. Due to the physical characteristics of NAND flash memory, the number of times that a block can be reliably erased is limited);
generate n erase pulses, where n is an integer that increases by 1 (Fig. 15A where it illustrates the integer number of erase pulse loops on the X-axis which increment by 1),
each erase pulse based on the baseline erase pulse parameter but without the desired amount of variation from the baseline erase pulse parameter (Fig. 15A where it illustrates the second and subsequent erase pulses incrementing at an amplitude different from the first pulse. It is noted that the instant application defines the “desired amount of variation” as apparently something applied to only the first erase pulse (Spec. para. 163). It is further noted that the term “desired amount of variation” has no defined characteristic with respect to the pulse. As noted in the indefiniteness rejection for claim 1 above, the phrase “desired amount of variation” will be interpreted to mean “an arbitrary value of pulse amplitude difference from the baseline initial erase voltage” and therefore “each erase pulse”, “without the desired amount of variation from the baseline erase pulse parameter” could therefore be any value that is not equal to the amplitude of the baseline initial erase voltage.);
Zhang is silent with respect to the express mechanism that determines how many erase pulse loops will be executed.
However, Takizawa teaches and apply the n erase pulses, one by one, until a threshold number of failed bits is exceeded (para 93; "... when the count of fail bits is larger than the specified value, the above-mentioned loop consisting of Erase -> Verify read -> First comparison -> Fail bit count -> Second comparison is ended, and a response which indicates failure of an erase operation (erase NG) is transmitted to the controller").
Zhang and Takizawa are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang’s modified erase pulses with the teachings of Takizawa’s erase loop termination mechanism. Doing so would more precisely set erase threshold voltages.
Regarding claim 2, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1,
As applied, Zhang further discloses wherein
the desired amount of variation from the baseline erase pulse parameter is selected to reduce an energy field across memory cells in the block of memory cells during the erase operation (col. 16, ln. 4-5; "For example, the different modes can involve a GIDL erase". It is noted that the term "reduce an energy field" appears to be directed to Fig. 13 (and spec. para. 196) in the instant application where it describes the technique of "GIDL erase”. It is noted that the same term "GIDL erase" is defined in the instant application (Spec. para. 131) with regard to inducing the same drain/gate carrier effect which is well known in the art).
Regarding claim 3, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1
As applied, Zhang further discloses wherein
the baseline erase pulse parameter comprises a baseline initial erase voltage (col. 2, ln. 18-21; "FIG. 14A depicts a plot of example erase voltages applied to a source line for a close block, where a baseline pulse width w1 and a baseline initial erase voltage Ver_init are used).
Regarding claim 4, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 3.
As applied, Zhang further discloses wherein
the first erase pulse comprises an erase voltage lower than the baseline initial erase voltage (Fig. 15A where it illustrates a first pulse with a voltage of Ver_init_low which is lower than the baseline erase pulse parameter Ver_init).
Regarding claim 5, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses wherein
the baseline erase pulse parameter comprises a baseline erase pulse width (col. 2, ln. 18-21; "FIG. 14A depicts a plot of example erase voltages applied to a source line for a close block, where a baseline pulse width w1 and a baseline initial erase voltage Ver_init are used).
Regarding claim 6, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 5.
As applied, Zhang further discloses wherein
the first erase pulse comprises an erase pulse width shorter than the baseline erase pulse width (Fig. 16A. See also col 2, ln 42-45; "FIG. 16A depicts a plot of example erase voltages applied to a source line for a close block, where a small pulse width w3<w1 and a baseline initial erase voltage Ver_init are used to provide a shallower erase").
Regarding claim 7, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses the first erase pulse comprises an erase voltage lower than a baseline initial erase voltage (Fig. 15A where it illustrates a first pulse with a voltage of Ver_init_low which is lower than the baseline erase pulse parameter Ver_init as one embodiment) and an erase pulse width shorter than a baseline erase pulse width (Fig. 16A as a second embodiment. See also col 2, ln 42-45; "FIG. 16A depicts a plot of example erase voltages applied to a source line for a close block, where a small pulse width w3<w1 and a baseline initial erase voltage Ver_init are used to provide a shallower erase").
While Zhang does not disclose a single embodiment with both limitations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang’s first embodiment with the teachings of Zhang’s second embodiment. Doing so would provide a more uniform erase depth which shortens the programming process and reduces program disturb (col. 5, ln. 3-6).
Regarding claim 8, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses wherein
the control circuit is further configured to perform an erase verify test on the block of memory cells (Fig. 10:S1012 ).
Regarding claim 9, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1
As applied, Zhang further discloses wherein
the control circuit is further configured to apply a second erase pulse to the block of memory cells without first performing an erase verify test on the block of memory cells (col. 15, ln. 34-36; "For example, this can involve deciding whether to apply an additional erase voltage without a verify test").
Regarding claim 11, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses wherein:
the baseline erase pulse parameter comprises a baseline initial erase voltage; (Fig. 14A:1401).
and the n erase pulses comprises an erase voltage equal to the baseline initial erase voltage plus an erase voltage step (Fig. 14A:1402).
Regarding claim 12, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses wherein:
the baseline erase pulse parameter comprises a baseline erase pulse width; (Fig. 14A:w1).
and the n erase pulses comprises an erase pulse width equal to the baseline erase pulse width (col. 19, ln12-15; "FIG. 14A depicts a plot of example erase voltages applied to a source line for a close block, where a baseline pulse width w1 and a baseline initial erase voltage Ver_init are used. It is noted that the baseline pulse width w1 is used on all pulses").
Regarding claim 13, Zhang and Takizawa combined as supported by Murugan disclose the limitations of claim 1.
As applied, Zhang further discloses wherein
the control circuit is further configured to apply erase pulses to the block of memory cells in a plurality of erase-verify iterations (Fig.10 which illustrates steps 1011-1013 and 1015 which is an erase-verify loop).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 9786378 – of Record) in view of Takizawa et al. (US 20170278581; “Takizawa”)
Regarding independent claim 15, notwithstanding the rejection for indefiniteness above, Zhang discloses an apparatus comprising:
a block of memory cells (Fig. 1A:126 array of memory cells);
and a control circuit coupled to the block of memory cells, the control circuit configured to perform an erase operation on the block of memory cells in a plurality of erase-verify loops (Fig. 1A:110 control circuitry. Fig. 10, step 1013 which shows an erase-verify loop performed),
wherein in a first erase-verify loop the control circuit is configured to apply a first erase pulse to the block of memory cells (Fig. 14A: 1401),
the first erase pulse comprising a parameter selected so that the first erase pulse does not erase the block of memory cells (col. 20, ln 19-21; "the initial erase voltage is lower. A result of this is that four erase loops are used instead of three to complete the erase operation". It is noted that since four erase loops are required, the first erase pulse necessarily does not erase the block.).
generate n erase pulses, where n is an integer that increases by 1 (Fig. 15A where it illustrates the integer number of erase pulse loops on the X-axis which increment by 1),
each erase pulse having a parameter based on the baseline erase pulse parameter but without the desired amount of variation from the baseline erase pulse parameter (Fig. 15A where it illustrates the second and subsequent erase pulses incrementing at an amount different from the first pulse. Also note discussion regarding the indefinite phrase “desired amount of variation” from claim 1 above);
Zhang is silent with respect to the express mechanism that determines how many erase pulse loops will be executed.
However, Takizawa teaches and apply the n erase pulses, one by one, until a threshold number of failed bits is exceeded (para 93; "... when the count of fail bits is larger than the specified value, the above-mentioned loop consisting of Erase -> Verify read -> First comparison -> Fail bit count -> Second comparison is ended, and a response which indicates failure of an erase operation (erase NG) is transmitted to the controller").
Zhang and Takizawa are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang’s modified erase pulses with the teachings of Takizawa’s erase loop termination mechanism. Doing so would more precisely set erase threshold voltages.
Regarding claim 16 and 17, Zhang and Takizawa combined disclose the limitations of claim 15.
As applied, Zhang further discloses wherein
the first erase pulse comprises an erase voltage (or pulse as per claim 17) that is selected to reduce an energy field across memory cells in the block of memory cells during the erase operation (col. 2, ln. 18-21; "FIG. 14A depicts a plot of example erase voltages applied to a source line for a close block, where a baseline pulse width w1 and a baseline initial erase voltage Ver_init are used. It is noted that the term "reduce an energy field" is interpreted in this instance to mean "lowering the floating gate threshold voltage". In the alternative however, it could also be interpreted to be a gate/drain effect of the GIDL erase technique of Zhang (see col. 16, ln. 4-5)).
Claim 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 9786378 – of Record) in view of Takizawa et al. (US 20170278581; “Takizawa”) as supported by C. Caillat et al. ("3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture"; “Caillat” – of Record).
Regarding independent claim 19, notwithstanding the rejection for indefiniteness above, Zhang discloses a method comprising:
performing an erase operation on a memory cell that is coupled to a select transistor by (Fig. 4 where it illustrates the memory cell with its gate terminal connected to WLD4 and its drain connected to select transistor SGS1. See also col. 6, ln 7-8; "An SGS transistor is a select gate transistor at a source end of a NAND string"):
applying a first drain erase pulse to a drain terminal of the select transistor while applying a first gate erase pulse to a gate terminal of the select transistor the first drain erase pulse comprising a first erase voltage selected to not erase the block of memory cells (col. 20, ln 19-21; "the initial erase voltage is lower. A result of this is that four erase loops are used instead of three to complete the erase operation". It is noted that since four erase loops are required, the first erase pulse necessarily does not erase the block)
and reduce an energy field across the memory cell (col. 16, ln. 4-5; "For example, the different modes can involve a GIDL erase". It is noted that the same term "GIDL erase" is defined in the instant application (Spec. para. 131) as it pertains to inducing the same drain/gate carrier effect which is well known in the art.);
and applying n drain erase pulses, where n is an integer that increases by 1, to the drain terminal of the select transistor while applying the first gate erase pulse to the gate terminal of the select transistor (As noted above, Zhang discloses the GIDL erase technique, which is well known in the art. While Zhang does not go into the details of multiple pulses, Caillat explains the effect of pulse duration for erase operation (Fig. 8 & Fig. 9) and the resultant increase in voltage differential across the gate to drain of the select transistor with increased duration (Verase has an inverse relationship with Vgd)),
the n drain erase pulses based on a baseline erase pulse and without the desired amount of variation from the first erase voltage the second erase voltage larger than the first erase voltage (Fig. 15A where it illustrates the first pulse 1501 initiating with an amplitude lower than the baseline erase pulse, and the second pulse 1502 at a higher amplitude than the first pulse. It is noted that the instant application defines the “desired amount of variation” as apparently something applied to only the first erase pulse (Spec. para. 163). It is further noted that the term “desired amount of variation” has no defined characteristic with respect to the pulse. As observed in the indefiniteness rejection for claim 1 above, the phrase “desired amount of variation” will be interpreted to mean “an arbitrary value of pulse amplitude difference from the baseline initial erase voltage” and therefore “each erase pulse”, “without the desired amount of variation from the baseline erase pulse parameter” could therefore be any value that is not equal to the amplitude of the baseline initial erase voltage.),
Zhang is silent with respect to the express mechanism that determines how many erase pulse loops will be executed.
However, Takizawa teaches the n rease [sic] pulses applied, one by one, until a threshold number of failed bits is exceeded (para 93; "... when the count of fail bits is larger than the specified value, the above-mentioned loop consisting of Erase -> Verify read -> First comparison -> Fail bit count -> Second comparison is ended, and a response which indicates failure of an erase operation (erase NG) is transmitted to the controller").
Zhang and Takizawa are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang’s modified erase pulses with the teachings of Takizawa’s erase loop termination mechanism. Doing so would more precisely set erase threshold voltages.
Regarding claim 20, Zhang and Takizawa combined as supported by Caillat disclose the limitations of claim 19
As applied, Zhang further discloses wherein
the first drain erase pulse and the second drain erase pulse generate a gate induced drain leakage current (col. 16, ln. 4-5; "For example, the different modes can involve a GIDL erase". It is noted that the same term "GIDL erase" is defined in the instant application (Spec. para. 131) with regard to inducing the same drain/gate carrier effect which is well known in the art.).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 9786378 – of Record) in view of Takizawa et al. (US 20170278581; “Takizawa”) and further in view of Bhat et al. (US 20220415403) as supported by Murugan et al. ("Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead"; “Murugan” – of Record).
Regarding claim 14, Zhang and Takizawa combined as supported by Murugan discloses the limitations of claim 1.
Zhang and Takizawa are silent with respect to a “stripe-erase” technique.
However, Bhat teaches the control circuit is further configured to:
in a first erase phase apply erase pulses to memory cells associated with every other word line of the block; and in a second erase phase apply erase pulses to memory cells associated with remaining word lines of the block (para. 56; “In many embodiments, the stripe-erase process 400 comprises a first step 410 of erasing the even word lines (shown as “even wl erase”), while the second step 450 comprises erasing the odd world lines (shown as “odd wl erase”)”).
Zhang and Takizawa combined along with Bhat are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Takizawa’s modified erase pulses with the teachings of Bhat’s striped erase process. Doing so would reduce overprogramming and increase the overall lifespan of the storage device (Absr.)
Response to Arguments
Applicant's arguments filed December 4, 2025, have been fully considered but they are not persuasive.
Applicant contends on pg. 3 of Remarks that the obviousness rejection of claim 1 is improper because Zhang does not disclose that “each n pulse after the first pulse is incremented without a desired variation from the baseline erase pulse” as claimed. To support their argument, applicant asserts that Zhang’s pulse step increments in Fig. 15A are the same.
Zhang does not explicitly disclose the step size of the pulses other than increasing in amplitude from Ver_init_low as can be discerned from Fig. 15A. However, as noted in the indefiniteness rejection of claim 1 above, the phrase “desired variation” is unclear. For purposes of examination, it is being interpreted to mean “an arbitrary value of pulse amplitude difference from the baseline initial erase voltage”. As such, Zhang’s erase pulse amplitudes of Fig. 15A read on the claim element and applicant has not demonstrated error in the findings presented in the rejection.
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Applicant further contends on pg. 3 of Remarks that the obviousness rejection of claim 1 is improper because Zhang fails to disclose “the first erase pulse does not erase the block of memory cells”. To support their argument, applicant asserts that Zhang’s first erase pulse “does erase” because Zhang recites that “ver_init_low is used to provide a shallower erase”, and “a shallower erase is not the same thing as not erasing at all”.
MPEP 2111.01 instructs that claims must be “given their broadest reasonable interpretation consistent with the specification." It is well understood in the art that for a block of memory cells to be erased, all their threshold voltages must be below the erase threshold value (See VvEr in Examiner’s Markup above). One of ordinary skill in the art would interpret the phrase “does not erase the block of memory cells” to mean that all the memory cells in the block are not fully erased. In other words, not simply precluding any act which would incrementally lower the threshold voltage of some of the memory cells (i.e.: the act of erasing), but instead preclude the completion of erasing the whole block.
While Zhang’s completed operation of a shallow erase would ultimately result in all the memory cells of the block being fully erased, the first of Zhang’s four erase pulses, while certainly lowering the threshold voltage value of at least some of the memory cells, would necessarily not be sufficient to result in lowering the threshold voltage of all the memory cells in the block below the erased value (VvEr)
Applicant further argues on pg. 3 of Remarks that independent claims 15 and 19 are patentable for the same reasons as claim 1. This argument is similarly not persuasive for the same reasons stated for independent claim 1. The rejection of all independent claims is therefore deemed proper and maintained.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825