Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-17 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 08/21/2023 ("08-21-23 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 08-21-23 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: STACKED WIRING STRUCTURE HAVING FIRST AND SECOND WIRING SUBSTRATE ELECTRICALLY CONNECTED BY FIRST AND SECOND CONDUCTIVE THROUGH VIAS
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 is indefinite, because it is unclear what “the at least one first dielectric layer” is referring to as there is no antecedent basis for it. For the purpose of advancing the examination of the instant application, "the at least one first dielectric layer" has been assumed to refer to "a plurality of first dielectric layers."
Claims 4 and 5 are indefinite, because it depends from the indefinite claim 3.
A. Prior-art rejections based on Yang
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patent No. US 10,840,190 B1 to Yang et al. (“Yang”).
Fig. 5B of Yang has been annotated to support the rejection below:
[AltContent: textbox (222)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (SUB2)][AltContent: textbox (SUB1)][AltContent: textbox (126)][AltContent: arrow][AltContent: textbox (220)][AltContent: arrow][AltContent: textbox (226)][AltContent: arrow][AltContent: ][AltContent: ]
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Regarding independent claim 1, Yang teaches a stacked wiring structure (see Fig. 5B as well as Figs. 1F and 2B) comprising:
a first wiring substrate SUB1, comprising a first glass substrate 126 (col. 3, ln 37-67 - “For example, the passivation layer 126′ is formed of…un-doped silicate glass…”) or 126, 120 (col. 3, ln 3-18 - “the interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate 110 and covering the semiconductor devices 112, and an inter-metallization dielectric (IMD) layer formed over the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG)…Spin-On-Glass...”), a plurality of first conductive through vias 152 (col. 7, ln 5-17 - “a plurality of conductive connectors 154”) penetrating through the first glass substrate 126 or 126, 120, and a first multi-layered redistribution wiring structure 122 (col. 3, ln 19-38 - “a plurality of interconnecting layers 122”) or 82, 84 (col. 17, ln 10-46 - “The redistribution structure 80 may include at least one conductive patterns 84 (e.g., lines, vias, pads) disposed in the dielectric pattern 82…”) disposed on the first glass substrate 126 or 126, 120; and
a second wiring substrate SUB2, comprising a second glass substrate 226 or 226, 220 (col. 9, ln 1-40 - “FIG. 2A and FIG. 2B are schematic cross-sectional views showing various stages in a manufacturing method of a tier of a semiconductor structure according to some exemplary embodiments of the present disclosure. The manufacturing method of the illustrated embodiment is similar to the manufacturing method of the tier TD1 described in FIG. 1A to FIG. 1F, and like elements throughout the drawings are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein…The interconnecting layers 222 and the dielectric layers 224 may be similar to the interconnecting layers 122 and the dielectric layers 124”), a plurality of second conductive through vias 152 penetrating through the second glass substrate 226 or 226, 220, and a second multi-layered redistribution wiring structure 222 disposed on the second glass substrate 226, wherein the first conductive through vias 152 are electrically connected to the second conductive through vias 152, the first glass substrate 126 or 126, 120 is spaced apart from the second glass substrate 226 or 226, 220, and the first multi-layered redistribution wiring structure 122 is spaced apart from the second multi-layered redistribution wiring structure 222 by the first glass substrate 126 or 126, 120 and the second glass substrate 226 or 226, 220.
Regarding claim 2, Yang teaches the first wiring substrate SUB1 that further comprises a plurality of first pads 154 (col. 7, ln 5-17 - “dummy connectors 152”), the second wiring substrate SUB2 that further comprises a plurality of second pads, and the first pads are connected to the second pads, so that the first glass substrate 126 is spaced apart from the second glass substrate 226 by a gap.
Regarding claim 3, Yang teaches the first multi-layered redistribution wiring structure 120 that comprises a plurality of first dielectric layers 124 and a plurality of first redistribution conducting wires 122 between the first dielectric layers 124, and
the second multi-layered redistribution wiring structure 220 that comprises at least one second dielectric layer 224, a plurality of second redistribution conducting wires 222, and a flat layer 110 (col. 3, ln 19-37 - “semiconductor substrate 110”) covering the at least one first dielectric layer 124 and the first redistribution conducting wires 122.
Regarding claim 8, Yang teaches a heater 112 (col. 2, ln 37-67 - “…the semiconductor devices 112 may be or may include active devices (e.g., transistors, diodes, etc.)…”; active device is reasonably capable of generating heat.), wherein the heater 112 is disposed in the first wiring substrate SUB1.
Regarding claim 9, Yang teaches a passive device 112 (col. 2, ln 37 - col. 3, ln 2 - “The semiconductor devices 112 may be or may include…passive devices…”), wherein the passive device 112 is disposed in the first wiring substrate SUB1.
B. Prior-art rejections based on Marin
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Patent No. US 2024/0063100 A1 to Marin et al. (“Marin”).
Fig. 2 of Marin as modified with package substrate 100 shown in annotated Fig. 1F have been provided to support the rejections below:
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[AltContent: arrow][AltContent: arrow][AltContent: textbox (P2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (P1)][AltContent: textbox (TV2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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Regarding independent claim 1, Marin teaches a stacked wiring structure, comprising:
a first wiring substrate 201 or 101 (para [0037] - “glass layers 201-203”; para [0022] - “The sublayers may comprise glass layers in some embodiments. In an embodiment, the sublayers may include a first layer 101, a second layer 102, and a third layer 103.”), comprising a first glass substrate 201 or 101, a plurality of first conductive through vias TV1 penetrating through the first glass substrate 201 or 101, and a first multi-layered redistribution wiring structure 271 (para [0037] - “In an embodiment, the electronic package 270 may further comprise one or more dielectric buildup layers 271 above and below the glass layers 201-203. The buildup layers may be formed with any standard buildup film or the like. The buildup layer 271 may include conductive features (not shown) such as pads, vias, traces, and the like. “) disposed on the first glass substrate 201 or 101; and
a second wiring substrate 203 or 103, comprising a second glass substrate 103 or 203, a plurality of second conductive through vias TV2 penetrating through the second glass substrate 103, and a second multi-layered redistribution wiring structure 271 disposed on the second glass substrate 103, wherein the first conductive through vias TV1 are electrically connected to the second conductive through vias TV2, the first glass substrate 201 or 101 is spaced apart from the second glass substrate 103 or 203, and the first multi-layered redistribution wiring structure 271 is spaced apart from the second multi-layered redistribution wiring structure 271 by the first glass substrate 202 or 101 and the second glass substrate 103 or 203.
Regarding claim 2, Marin teaches the first wiring substrate 201 or 101 that further comprise a plurality of first pads P1, the second wiring substrate 203 or 103 that further comprises a plurality of second pads P2, and the first pads P1 are connected to the second pads P2, so that the first glass substrate 201 or 101 is spaced apart from the second glass substrate 203 or 103 by a gap.
Regarding claim 10, Marin teaches a plurality of solder balls 151, wherein the solder balls 151 are electrically connected between the first conductive through vias TV1 and the second conductive through vias TV2, so that the first glass substrate 201 or 101 is spaced apart from the second glass substrate 203 or 103 by a gap.
C. Prior-art rejections based on Pietambaram
Claim Rejections - 35 USC § 102
Claims 11-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Patent No. US 2023/0080454 A1 to Pietambaram et al. (“Pietambaram”).
Fig. 4 of Pietambaram has been annotated and Fig. 1A of Pietambaram has been provided to support the rejections below:
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Regarding independent claim 11, Pietambaram teaches a stacked wiring structure (see Fig. 4; see also Fig. 1A), comprising:
a first wiring substrate 402 (para [0097] - “package substrate 402”; para [0094] - “core 404 may comprise glass fiber reinforced epoxy, such as fire-retardant grade 4 (FR-4) glass epoxy with thin copper foil laminated on either side. In some embodiments, core 404 may additionally include prepreg.”), comprising an organic substrate 404, a plurality of conducting wires 410 (para [0097] - “Inductors 410 may comprise coaxial magnetic inductors layer (MIL) structure embedded within core 404 of package substrate 402. In some embodiments, the coaxial MIL structure may include a copper-lined plated through-hole (PTH) surrounded by a high permeability magnetic material such as magnetic resin.”) penetrating through the organic substrate 404, and a first multi-layered redistribution wiring structure 408 or 408, 406 (para [0094] - “insulator 406 and conductive pathways 408”) disposed on the organic substrate 404; and
a second wiring substrate 102 (para [0072] - “a substrate 102 having a core 104”), comprising a glass substrate 104 (para [0072] - “Core 104 comprises bulk transparent glass, which is different from fiberglass (e.g., as in fiberglass reinforced epoxy cores typically used in package substrates or motherboards) and opaque polycrystalline ceramic glass (e.g., which are used in high-temperature applications).”), a plurality of conductive through vias 120 (para [0077] - “TGVs 120 in core 104”) penetrating through the glass substrate 104, and a second multi-layered redistribution wiring structure 126 or 126, 124, 122 (para [0078] - “…A second dielectric 124 may comprise the same material as first dielectric 122…conductive traces 126, including vias, planes and pads…”) disposed on the glass substrate 104, wherein the conducting wires 410 are electrically connected to the conductive through vias 120, and the organic substrate 404 is spaced apart from the glass substrate 104.
Regarding claim 12, Pietambaram teaches a probe head 130, 128 (para [0080] - “An optical lens 130 of approximately similar diameter as optical via 128”) with a probe 128, wherein the probe head 130, 128 is disposed above the second wiring substrate 102.
Regarding claim 13, Pietambaram teaches the first wiring substrate 402 that further comprises a plurality of first pads P1, the second wiring substrate 102 further comprises a plurality of second pads 142 (para[0083] - “MLI 142”; see Fig. 1A), and the first pads P1 are connected to the second pads 142, so that the organic substrate 404 is spaced apart from the glass substrate 104 by a gap.
Regarding claim 14, Pietambaram teaches the first multi-layered redistribution wiring structure 408, 406 that comprises at least one first dielectric layer 406 and a plurality of first redistribution conducting wires 408.
Regarding claim 15, Pietambaram teaches the second multi-layered wiring structure 126, 124, 122 that further comprises a stress control layer 122 (The dielectric materials for the second dielectric 124 as disclosed in para [0078] are reasonably capable of providing the function of stress control as polymers are more likely than not to be pliant than glass.), and the stress control layer 122 is disposed on the glass substrate 104, in the second multi-layered redistribution wiring structure 126, 124, 122 and/or on the second multi-layered redistribution wiring structure 126, 124, 122.
Regarding claim 16, Pietambaram teaches a heater 114 (para [0077] - “one or more IC die 114”; an IC dies is reasonably capable of generating heat when operating.), wherein the heater 114 is disposed in the second wiring substrate 102.
Regarding claim 17, Pietambaram teaches a passive device 410 (para [0097] - “inductors 410 may comprise coaxial magnetic inductors layer (MIL) structure embedded within core 404 of the package substrate 402”), wherein the passive device 410 is disposed in the first wiring substrate 402.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 6.
Claim 7 is allowable for depending on the allowable claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2023/0260945 A1 to Wu et al.
Pub. No. US 2023/0378092 A1 to Lai et al.
Pub. No. US 2023/0063304 A1 to Liu et al.
Pub. No. US 2021/0280505 A1 to Huang
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 08 November 2025
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status