DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/3/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352 and further in view of OH, US 2021/0375901.
Regarding claims 1-2, OH discloses of claim 1; a semiconductor device comprising: a first semiconductor structure including a stack (Fig. 4-5 and [0068]; cell structure CS) including an step structure (Fig. 4-5 and [0078]; electrode layers 30 and interlayer dielectric layers 32, which are alternately stacked and formed staircase in the cell structure CS), a source structure (Fig. 4-5 and [0078]; cell structure CS include a source plate 20) located below the stack, a bit line (Fig. 4-6 and [0084]; bit lines BL) located above the stack, and channel structures (Fig. 5 and [0078]; vertical channels CH) extending through the stack; a second semiconductor structure (Fig. 4-5 and [0068]; a logic structure LS bonded with cell structure CS) bonded to the first semiconductor structure, and the second semiconductor structure including a) pass transistors (Fig. 4-5 and [0070]; pass transistor circuit 121) located to face a lower surface of the step structure and b) a first peripheral circuit (Fig. 2-5 and [0062]; pass transistor circuit 121 include a plurality of pass transistor groups PASS TR GROUP having peripheral circuit) located to face a lower surface of the source structure; and a third semiconductor structure (Fig. 4-5 and [0068]; second wafer WF2) bonded to the first semiconductor structure, and the third semiconductor structure including a) a page buffer (Fig. 4-5 and [0070]; page buffer circuit 130 to face bit line BL) located to face an upper surface of the bit line and b) a second peripheral circuit (Fig. 4-5 and [0070]; peripheral circuit 140 and a block switch circuit 122) located to face an upper surface of the step structure. wherein the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure in the vertical direction (Fig. 4-5 and [0068]; cell structure CS disposed between logic structure LS and second wafer WF2 in vertical direction), and wherein the second semiconductor structure is bonded to a first surface of the first semiconductor structure (Fig. 4-5 and [0068]; logic structure LS bonded to the top surface of cell structure CS), and the third semiconductor structure is bonded to a second surface of the first semiconductor structure opposite to the first surface (Fig. 4-5 and [0068]; second wafer WF2 bonded to the bottom surface of cell structure CS).
Regarding claim 2, OH discloses; the stack includes conductive layers respectively exposed (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) through the step structure.
OH substantially discloses the claimed invention of semiconductor device with step structure having a bit line located on top and source plate located below but is silent about the step structure is inverted in claims 1-2. However, Simsek-Ege shows the inverted step structure (Fig. 3C, 4C; the lower three steps 375 of the staircase structure 374 are inverted compare to the global digit lines 308, which is referred as a bit line [0035]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH by providing the inverted step structure, as taught by Simsek-Ege, so that within horizontal boundaries of each of the staircase structures facilitates formation of electrical connections for the sub word line driver circuitry within a smaller area compared to conventional microelectronic devices ([0167]) and for forming the microelectronic device to exhibit a reduced horizontal area (e.g., footprint) and an increased memory density compared to conventional microelectronic devices ([0024]). OH, in view of Simsek-Ege substantially discloses the claimed invention of semiconductor device with page buffer circuit and pass transistor circuit but is silent about the page buffer is at least partially overlapped with the pass transistors in a vertical direction. However, OH’901 teaches that the pass transistor circuit PASS_TR overlap with the page buffer circuit PBC in the vertical direction VD (Fig.4-5 and [0065]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH, in view of Simsek-Ege by providing the page buffer is at least partially overlapped with the pass transistors in a vertical direction, as taught by OH’901, to increasing the layout utilization efficiency of a memory device and reducing the size of the memory device ([0004]).
Regarding claim 3, OH discloses; first contact plugs connected (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) to the conductive layers, respectively.
Regarding claim 4, OH discloses; the conductive layers and the pass transistors are electrically connected (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) to each other through the first contact plugs.
Regarding claim 5, OH discloses; the first peripheral circuit includes a voltage generator that transmits voltage to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 and provided with an operating voltage from the pass transistor circuit 121).
Regarding claim 6, OH discloses; the second peripheral circuit includes a data input/output circuit or a logic circuit that controls the page buffer (Fig. 4-5 and [0038]; page buffer circuit 130 receives a page buffer control signal PBCON from the peripheral circuit 140 and transmit and receive a data signal DATA to and from the peripheral circuit 140).
Regarding claim 7, OH discloses; a second contact plug that extends through the first semiconductor structure and electrically connects (Fig. 4-5 and [0091]; an electrical path that couples the external coupling pad EPAD and the peripheral circuit 140 and an electrical path that couples the pass transistor circuit 121 and the block switch circuit 122 connects between logic structure LS and second wafer WF2) the second semiconductor structure and the third semiconductor structure.
Regarding claim 8, OH discloses; the first semiconductor structure includes a first bonding pad (Fig. 4-5 and [0078]; bonding pads on source plate 20 at cell structure CS) located below the source structure and a second bonding pad (Fig. 4-5 and [0089]; bonding pads PAD1 configured in the second wiring layer M2 on the bit lines BL at cell structure CS) located above the bit line.
Regarding claim 9, OH discloses; wherein the second semiconductor structure includes a third bonding pad (Fig. 4-5 and [0078]; bonding pads at logic structure LS connects with source plate 20 at cell structure CS) bonded to the first bonding pad.
Regarding claim 10, OH discloses; the third semiconductor structure includes a fourth bonding pad (Fig. 4-5 and [0090-0091]; second wafer WF2 include a plurality of second bonding pads PAD2 bonded to a corresponding first bonding pad PAD1) bonded to the second bonding pad.
Regarding claim 11, OH discloses; each of the pass transistors is a high voltage transistor (Fig. 4-5 and [0036]; the pass transistor circuit 121 transfer an operating voltage Vop from the peripheral circuit 140; examiner interpret “high” as a relative term).
Claim(s) 12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352.
Regarding claim 12, OH discloses; a semiconductor device comprising: pass transistors (Fig. 4-5 and [0070]; pass transistor circuit 121); a first bonding structure (attached Fig. 5 below) located over the pass transistors; a first interconnection structure (attached Fig. 5 below) located between the pass transistors and the first bonding structure and the first interconnection structure connecting (attached Fig. 5 below) the first bonding structure and the pass transistors; a stack (Fig. 4-5 and [0068]; cell structure CS) located over the first bonding structure and the stack including an step structure (Fig. 4-5 and [0078]; electrode layers 30 and interlayer dielectric layers 32, which are alternately stacked and formed staircase in the cell structure CS) and conductive layers respectively exposed (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) through the step structure; a bit line (Fig. 4-6 and [0084]; bit lines BL) located above the stack; first contact plugs located below the step structure and connected to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase), respectively, and the first contact plugs being arranged at positions diagonally crossing (attached Fig. 5 below) the bit line; a second bonding structure (attached Fig. 5 below) located over the bit line; a page buffer (Fig. 4-5 and [0070]; page buffer circuit 130 to face bit line BL) located over the second bonding structure and facing an upper surface of the bit line; and a second interconnection structure (attached Fig. 5 below) located between the page buffer and the second bonding structure and the second interconnection structure connecting (attached Fig. 5 below) the second bonding structure and the page buffer. wherein the stack is interposed between the first bonding structure and the second bonding structure in a vertical direction (attached Fig. 5 below), and wherein the first contact plugs are disposed between the conductive layers and the first bonding structure (attached Fig. 5 below), and the bit line is disposed between the stack and the second bonding structure (attached Fig. 5 below). OH substantially discloses the claimed invention of semiconductor device with step structure having a bit line located on top and source plate located below but is silent about the step structure is inverted in claims 1-2. However, Simsek-Ege shows the inverted step structure (Fig. 3C, 4C; the lower three steps 375 of the staircase structure 374 are inverted compare to the global digit lines 308, which is referred as a bit line [0035]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH by providing the inverted step structure, as taught by Simsek-Ege, so that within horizontal boundaries of each of the staircase structures facilitates formation of electrical connections for the sub word line driver circuitry within a smaller area compared to conventional microelectronic devices ([0167]) and for forming the microelectronic device to exhibit a reduced horizontal area (e.g., footprint) and an increased memory density compared to conventional microelectronic devices ([0024]).
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Regarding claim 14, OH discloses; the conductive layers and the pass transistors are electrically connected to each other through the first contact plugs the first bonding structure, and the first interconnection structure (attached Fig. 5 above; electrode layers 30 electrically coupled to the pass transistor circuit 121 through the first contact plugs the first bonding structure, and the first interconnection structure) and wherein the first contact plugs are disposed adjacent to the pass transistors in the vertical direction with the first bonding structure disposed therebetween (attached Fig. 5 above).
Regarding claim 15, OH discloses; the bit line and the page buffer are electrically connected to each other through the second bonding structure and the second interconnection structure (Fig. 4-6, [0070, 0084] and attached Fig. 5 above; bit lines BL and page buffer circuit 130 are electrically connected through the second bonding structure and the second interconnection structure) wherein the bit line, the second bonding structure, the second interconnection structure, and the page buffer are sequentially arranged in the vertical direction (attached Fig. 5 above).
Regarding claim 16, OH discloses; a first peripheral circuit (Fig. 2-5 and [0062]; pass transistor circuit 121 include a plurality of pass transistor groups PASS TR GROUP having peripheral circuit) located below the first bonding structure, and the first peripheral circuit includes a voltage generator that transmits a voltage to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121, and provided with an operating voltage from the pass transistor circuit 121).
Regarding claim 17, OH discloses; a second peripheral circuit (Fig. 4-5; [0070] and attached Fig. 5 above; peripheral circuit 140 and a block switch circuit 122 located above PAD1,PAD2) located over the second bonding structure, and the second peripheral circuit includes a data input/output circuit or a logic circuit that controls the page buffer (Fig. 4-5 and [0038]; page buffer circuit 130 receive a page buffer control signal PBCON from the peripheral circuit 140, and transmit and receive a data signal DATA to and from the peripheral circuit 140).
Regarding claim 18, OH discloses; a second contact plug that electrically connects (Fig. 4-5, [0091] and attached Fig. 5 above; an electrical path that couples the external coupling pad EPAD and the peripheral circuit 140 and an electrical path that couples the pass transistor circuit 121 and the block switch circuit 122 connects between first and second bonding structure) the first bonding structure and the second bonding structure.
Regarding claim 19, OH discloses; each of the pass transistors is a high voltage transistor (Fig. 4-5 and [0036]; the pass transistor circuit 121 transfer an operating voltage Vop from the peripheral circuit 140; examiner interpret “high” as a relative term).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352 and further in view of OH, US 2021/0375901.
Regarding claim 13, OH, in view of Simsek-Ege substantially discloses the claimed invention of semiconductor device with page buffer circuit and pass transistor circuit but is silent about the page buffer is at least partially overlapped with the pass transistors in a vertical direction. However, OH’901 teaches that the pass transistor circuit PASS_TR overlap with the page buffer circuit PBC in the vertical direction VD (Fig.4-5 and [0065]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH, in view of Simsek-Ege by providing the page buffer is at least partially overlapped with the pass transistors in a vertical direction, as taught by OH’901, to increasing the layout utilization efficiency of a memory device and reducing the size of the memory device ([0004]).
Response to Arguments
Applicant's arguments filed 7/3/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that the cited reference(s) fails to render obvious the claimed invention and thus, the claimed invention is distinguishable over the cited reference(s), the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, OH, US 2023/0111844, taking the teachings of Simsek-Ege, US 2023/0411352 and OH, US 2021/0375901. Also test for combining references is what the combination of disclosures taken as a whole would be suggest to one of ordinary skill in the art.
Regarding applicant’s argument that “Oh is directed to a two-wafer bonded structure in which a first wafer W1 and a second wafer W2 are bonded to each other. Oh '901 does not disclose or suggest a structure in which a second semiconductor structure including the pass transistors and a third semiconductor structure including the page buffer are separately bonded to opposite surfaces of the first semiconductor structure. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., separately bonded) are not recited in the rejected claim(s). Also, in Fig. 4 of OH ‘844 clearly shows that layer CS and LS bonded together to form the wafer WF1. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's arguments a prima facie case of obviousness has not been established under 35 U.S.C. § 103 with respect to independent claim 1 and its dependent claims. However, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Regarding applicant’s argument about claim 12, examiner in the rejection above shown that the first contact plugs are disposed between the conductive layers and the first bonding structure in horizontal/ second SD direction. Therefore, applicant’s argument is unsound.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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