DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. New Claims 14 and 15 have claim language “a minimized connection path”, though applicant argued that support for the new claims at least be found in the originally filed drawings at FIG. 2 and accompanying portion of the original specification, however the examiner couldn’t find the claim language “a minimized connection path” in the specification. Accordingly, the claim language “a minimized connection path” of new claims 14-15 is a new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
New Claims 14 and 15 have claim language “a minimized connection path”, though applicant argued that support for the new claims at least be found in the originally filed drawings at FIG. 2 and accompanying portion of the original specification, however the examiner couldn’t find the claim language “a minimized connection path” in the specification. Accordingly, the scope of the claim language “a minimized connection path” of new claims 14-15 is unclear and indefinite as specification does not clarify the term. Also, as “minimized” is a relative term of degree used in the past tense, as such the claim language attempts to claim a path minimized or shortened from some reference path. Since no other path is claimed or any standard for measuring the term of degree, it is not clear how one of ordinary skill in the art will determine if a connection path is a minimized connection path. For purposes of prior art rejections below, a minimized connection path is being interpreted as direct electrical connection between circuit elements with minimum length of the path.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352 and further in view of OH, US 2021/0375901.
Regarding claims 1-2, OH discloses of claim 1; a semiconductor device comprising: a first semiconductor structure including a stack (Fig. 4-5 and [0068]; cell structure CS) including an step structure (Fig. 4-5 and [0078]; electrode layers 30 and interlayer dielectric layers 32, which are alternately stacked and formed staircase in the cell structure CS), a source structure (Fig. 4-5 and [0078]; cell structure CS include a source plate 20) located below the stack, a bit line (Fig. 4-6 and [0084]; bit lines BL) located above the stack, and channel structures (Fig. 5 and [0078]; vertical channels CH) extending through the stack; a second semiconductor structure (Fig. 4-5 and [0068]; a logic structure LS bonded with cell structure CS) bonded to the first semiconductor structure, and the second semiconductor structure including a) pass transistors (Fig. 4-5 and [0070]; pass transistor circuit 121) located to face a lower surface of the step structure and b) a first peripheral circuit (Fig. 2-5 and [0062]; pass transistor circuit 121 include a plurality of pass transistor groups PASS TR GROUP having peripheral circuit) located to face a lower surface of the source structure; and a third semiconductor structure (Fig. 4-5 and [0068]; second wafer WF2) bonded to the first semiconductor structure, and the third semiconductor structure including a) a page buffer (Fig. 4-5 and [0070]; page buffer circuit 130 to face bit line BL) located to face an upper surface of the bit line and b) a second peripheral circuit (Fig. 4-5 and [0070]; peripheral circuit 140 and a block switch circuit 122) located to face an upper surface of the step structure.
Regarding claim 2, OH discloses; the stack includes conductive layers respectively exposed (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) through the step structure.
OH substantially discloses the claimed invention of semiconductor device with step structure having a bit line located on top and source plate located below but is silent about the step structure is inverted in claims 1-2. However, Simsek-Ege shows the inverted step structure (Fig. 3C, 4C; the lower three steps 375 of the staircase structure 374 are inverted compare to the global digit lines 308, which is referred as a bit line [0035]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH by providing the inverted step structure, as taught by Simsek-Ege, so that within horizontal boundaries of each of the staircase structures facilitates formation of electrical connections for the sub word line driver circuitry within a smaller area compared to conventional microelectronic devices ([0167]) and for forming the microelectronic device to exhibit a reduced horizontal area (e.g., footprint) and an increased memory density compared to conventional microelectronic devices ([0024]). OH, in view of Simsek-Ege substantially discloses the claimed invention of semiconductor device with page buffer circuit and pass transistor circuit but is silent about the page buffer is at least partially overlapped with the pass transistors in a vertical direction. However, OH’901 teaches that the pass transistor circuit PASS_TR overlap with the page buffer circuit PBC in the vertical direction VD (Fig.4-5 and [0065]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH, in view of Simsek-Ege by providing the page buffer is at least partially overlapped with the pass transistors in a vertical direction, as taught by OH’901, to increasing the layout utilization efficiency of a memory device and reducing the size of the memory device ([0004]).
Regarding claim 3, OH discloses; first contact plugs connected (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) to the conductive layers, respectively.
Regarding claim 4, OH discloses; the conductive layers and the pass transistors are electrically connected (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) to each other through the first contact plugs.
Regarding claim 5, OH discloses; the first peripheral circuit includes a voltage generator that transmits a voltage to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121, and provided with an operating voltage from the pass transistor circuit 121).
Regarding claim 6, OH discloses; the second peripheral circuit includes a data input/output circuit or a logic circuit that controls the page buffer (Fig. 4-5 and [0038]; page buffer circuit 130 receive a page buffer control signal PBCON from the peripheral circuit 140, and transmit and receive a data signal DATA to and from the peripheral circuit 140).
Regarding claim 7, OH discloses; a second contact plug that extends through the first semiconductor structure and electrically connects (Fig. 4-5 and [0091]; an electrical path that couples the external coupling pad EPAD and the peripheral circuit 140 and an electrical path that couples the pass transistor circuit 121 and the block switch circuit 122 connects between logic structure LS and second wafer WF2) the second semiconductor structure and the third semiconductor structure.
Regarding claim 8, OH discloses; the first semiconductor structure includes a first bonding pad (Fig. 4-5 and [0078]; bonding pads on source plate 20 at cell structure CS) located below the source structure and a second bonding pad (Fig. 4-5 and [0089]; bonding pads PAD1 configured in the second wiring layer M2 on the bit lines BL at cell structure CS) located above the bit line.
Regarding claim 9, OH discloses; wherein the second semiconductor structure includes a third bonding pad (Fig. 4-5 and [0078]; bonding pads at logic structure LS connects with source plate 20 at cell structure CS) bonded to the first bonding pad.
Regarding claim 10, OH discloses; the third semiconductor structure includes a fourth bonding pad (Fig. 4-5 and [0090-0091]; second wafer WF2 include a plurality of second bonding pads PAD2 bonded to a corresponding first bonding pad PAD1) bonded to the second bonding pad.
Regarding claim 11, OH discloses; each of the pass transistors is a high voltage transistor (Fig. 4-5 and [0036]; the pass transistor circuit 121 transfer an operating voltage Vop from the peripheral circuit 140; examiner interpret “high” as a relative term).
Claim(s) 12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352.
Regarding claim 12, OH discloses; a semiconductor device comprising: pass transistors (Fig. 4-5 and [0070]; pass transistor circuit 121); a first bonding structure (attached Fig. 5 below) located over the pass transistors; a first interconnection structure (attached Fig. 5 below) located between the pass transistors and the first bonding structure and the first interconnection structure connecting (attached Fig. 5 below) the first bonding structure and the pass transistors; a stack (Fig. 4-5 and [0068]; cell structure CS) located over the first bonding structure and the stack including an step structure (Fig. 4-5 and [0078]; electrode layers 30 and interlayer dielectric layers 32, which are alternately stacked and formed staircase in the cell structure CS) and conductive layers respectively exposed (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase) through the step structure; a bit line (Fig. 4-6 and [0084]; bit lines BL) located above the stack; first contact plugs located below the step structure and connected to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase), respectively, and the first contact plugs being arranged at positions diagonally crossing (attached Fig. 5 below) the bit line; a second bonding structure (attached Fig. 5 below) located over the bit line; a page buffer (Fig. 4-5 and [0070]; page buffer circuit 130 to face bit line BL) located over the second bonding structure and facing an upper surface of the bit line; and a second interconnection structure (attached Fig. 5 below) located between the page buffer and the second bonding structure and the second interconnection structure connecting (attached Fig. 5 below) the second bonding structure and the page buffer. OH substantially discloses the claimed invention of semiconductor device with step structure having a bit line located on top and source plate located below but is silent about the step structure is inverted in claims 1-2. However, Simsek-Ege shows the inverted step structure (Fig. 3C, 4C; the lower three steps 375 of the staircase structure 374 are inverted compare to the global digit lines 308, which is referred as a bit line [0035]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH by providing the inverted step structure, as taught by Simsek-Ege, so that within horizontal boundaries of each of the staircase structures facilitates formation of electrical connections for the sub word line driver circuitry within a smaller area compared to conventional microelectronic devices ([0167]) and for forming the microelectronic device to exhibit a reduced horizontal area (e.g., footprint) and an increased memory density compared to conventional microelectronic devices ([0024]).
PNG
media_image1.png
800
797
media_image1.png
Greyscale
Regarding claim 14, OH discloses; the conductive layers and the pass transistors are electrically connected to each other through the first contact plugs along a minimized connection path (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121 at the staircase through the direct minimum length of the path).
Regarding claim 15, OH discloses; the bit line and the page buffer are electrically connected to each other through the second interconnection structure along a minimized connection path (Fig. 4-6, [0070, 0084] and attached Fig. 5 above; bit lines BL and page buffer circuit 130 are electrically connected through the direct minimum length of the path).
Regarding claim 16, OH discloses; a first peripheral circuit (Fig. 2-5 and [0062]; pass transistor circuit 121 include a plurality of pass transistor groups PASS TR GROUP having peripheral circuit) located below the first bonding structure, and the first peripheral circuit includes a voltage generator that transmits a voltage to the conductive layers (Fig. 4-5 and [0081]; electrode layers 30 electrically coupled to the pass transistor circuit 121, and provided with an operating voltage from the pass transistor circuit 121).
Regarding claim 17, OH discloses; a second peripheral circuit (Fig. 4-5; [0070] and attached Fig. 5 above; peripheral circuit 140 and a block switch circuit 122 located above PAD1,PAD2) located over the second bonding structure, and the second peripheral circuit includes a data input/output circuit or a logic circuit that controls the page buffer (Fig. 4-5 and [0038]; page buffer circuit 130 receive a page buffer control signal PBCON from the peripheral circuit 140, and transmit and receive a data signal DATA to and from the peripheral circuit 140).
Regarding claim 18, OH discloses; a second contact plug that electrically connects (Fig. 4-5, [0091] and attached Fig. 5 above; an electrical path that couples the external coupling pad EPAD and the peripheral circuit 140 and an electrical path that couples the pass transistor circuit 121 and the block switch circuit 122 connects between first and second bonding structure) the first bonding structure and the second bonding structure.
Regarding claim 19, OH discloses; each of the pass transistors is a high voltage transistor (Fig. 4-5 and [0036]; the pass transistor circuit 121 transfer an operating voltage Vop from the peripheral circuit 140; examiner interpret “high” as a relative term).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352 and further in view of OH, US 2021/0375901.
Regarding claim 13, OH, in view of Simsek-Ege substantially discloses the claimed invention of semiconductor device with page buffer circuit and pass transistor circuit but is silent about the page buffer is at least partially overlapped with the pass transistors in a vertical direction. However, OH’901 teaches that the pass transistor circuit PASS_TR overlap with the page buffer circuit PBC in the vertical direction VD (Fig.4-5 and [0065]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify OH, in view of Simsek-Ege by providing the page buffer is at least partially overlapped with the pass transistors in a vertical direction, as taught by OH’901, to increasing the layout utilization efficiency of a memory device and reducing the size of the memory device ([0004]).
Response to Arguments
Amendments to the specification with substitute specification sent on 03/05/2026 has been accepted
Applicant’s arguments with respect to claim(s) 1-11have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding applicant’s argument about amended independent claim 1, new 103 rejection with new set of references such as OH, US 2023/0111844, in view of Simsek-Ege, US 2023/0411352 and further in view of OH, US 2021/0375901 has been applied, please see the rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW RICHARDS can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights