DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/ Restriction
2. Applicant's election with traverse of Invention I, claims 1-15, and withdrawal of claims 16-20, in the reply filed on 11/28/2025 is acknowledged. The traversal is on the ground(s) that there is no serious burden upon the Examiner in searching and examining all the claims of both the inventions. This is not found persuasive because, as is clear in the rejections below, reference(s) found during the allotted search applicable to the elected invention is not applicable to the other invention, and it would have imposed serious burden upon the examiner for searching and examining the claims of the other invention.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. U.S. Patent Application Publication 2023/0008409 A1 (the ‘409 reference).
The reference discloses in Fig. 12B and related text a semiconductor device as claimed.
Referring to claim 1, the ‘409 reference discloses a semiconductor device, comprising:
a substrate (100, para [20]);
two-dimensional material layers (126 (126A, 126B, 126C), para [33, 41 (paragraph(s) [0033], [0041])), which may be termed complex two-dimensional material layers as claimed, disposed over the substrate, wherein the complex two-dimensional material layers (126) are arranged spaced apart from one each other and in parallel to one another;
a gate structure (190, including metal fills 194, para [51], see Fig. 9B), disposed across and wrapping around and surrounding (para [75]) first portions of the complex two-dimensional material layers (126); and
source and drain regions (210N, para [59]), disposed on opposite sides of the gate structure and wrapping around and surrounding second portions (1262) of the complex two-dimensional material layers (126).
Referring to claim 5, the reference further discloses sidewall spacers (170 or 170/182, para [44, 45], see also Fig. 8C) disposed between the gate structure (190) and source and drain regions (210N).
Referring to claim 6, the reference further discloses that each of the sidewall spacers (170/182) includes a first spacer (182) and a second spacer (170) disposed on the first spacer, and the second spacer (170) is made of a material (silicon oxide, para [44]) different from that of the first spacer (formed of a high dielectric constant material such as hafnium oxide, para [48]).
Referring to claim 7, for the device detailed above for claim 5, the reference further discloses that the gate structure includes a gate dielectric layer (182, para [45], see also Fig. 8C) and a gate metallic layer (194, para [51]), and the gate dielectric layer (182) is in contact with the sidewall spacers (170).
Referring to claim 8, for the device detailed above for claim 1 the reference further discloses lateral inner spacers (170, para [44]) located between the gate structure (190) and the source and drain regions (210N).
Allowable Subject Matter
4. Claims 9-15 are allowable over the prior art of record.
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor device and a structure with all exclusive limitations as recited in claims 2 and 9, which may be characterized (claim 2) in that first portions of the complex two-dimensional material layers include a transition metal dichalcogenide material, and the second portions of the complex two-dimensional material layers include graphene, and (claim 9) in that the channel portions are made of a first two-dimensional material different from a second two-dimensional material of the extended portions.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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02-17-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818