CTNF 18/452,616 CTNF 99314 Attorney Docket Number: S2329.70761US00 Filing Date: 08/21/2023 Claimed Priority Date: 12/06/2022 (KR 10-2022-0168846) Inventors: Yang et al. Examiner: Shamita S. Hanumasagar DETAILED ACTION This Office action responds to the election filed on 02/18/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis ( i.e. , changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Elections/Restrictions Applicant’s election without traverse of Species 4, reading on figures 1 and 3-4 in view of figures 6 and 8, in the reply filed on 02/18/2026, is acknowledged. The applicant indicated that claims 1-9 and 16-20 read on the elected species. The examiner agrees. Accordingly, claims 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected species, there being no allowable generic or linking claim. Initial Remarks For all instances of “Annotated Fig. 2”, please refer to the following image below, which is an enlarged and marked portion of figure 2 of Lee (US 2020/0381393). No other changes have been made to the figure. PNG media_image1.png 578 1213 media_image1.png Greyscale Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 3-6, 9, and 20 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 3 recites the limitation “wherein each of the memory dies includes a through via region” before reciting the limitation “wherein at least a portion of the first die overlaps the through via regio n ”. It is unclear to which specific via region of the previously recited plurality of via regions the limitation “the through via region” is intended to refer. Accordingly, this limitation in the claim is indefinite as it is unclear to which of the many previously recited through via regions the limitation “ the through via regio n ” refers. Claim 4 recites the limitation “where a width of the first die is greater than a width of the through via region ”. Parental claim 3, however, recites the limitation “wherein each of the memory dies includes a through via region”. It is unclear to which specific via region of the previously recited plurality of via regions the limitation “the through via region” is intended to refer. Accordingly, this limitation in claim 4 is indefinite as it is unclear to which of the many previously recited through via regions the limitation “ the through via regio n ” refers. Claim 5 recites the limitation “wherein the through via region is between the first cell region and the second cell region”. Parental claim 3, however, recites the limitation “wherein each of the memory dies includes a through via region”. It is unclear to which specific via region of the previously recited plurality of via regions the limitation “the through via region” is intended to refer. Accordingly, this limitation in claim 5 is indefinite as it is unclear to which of the many previously recited through via regions the limitation “ the through via regio n ” refers. Claim 6 recites the limitations “wherein a side surface of the first die overlaps the first cell region in the vertical direction” and “wherein a second side surface of the first die… overlaps the second cell region in the vertical region”. Parental claim 5, however, recites the limitation “wherein each of the memory dies includes a first cell region and a second cell region”, indicating a plurality of first and second cell regions across the plurality of memory dies. It is unclear to which specific first and second cell region of the previously recited plurality of first and second cell regions the limitations “the first cell region” and “the second cell region” are intended to refer. Accordingly, these limitations in claim 6 are indefinite as it is unclear to which of the many previously recited first and second cell regions the limitations “ the first cell regio n ” and “ the second cell regio n ” refer. Claim 9 recites the limitation “wherein a minimum pitch of a gate electrode of the first die is smaller than a minimum pitch of a gate electrode of the second die”. As understood in the art and as is consistent with the written description, “pitch” describes a spacing measurement between multiple objects or features. Claim 9 and parental claim 1, however, do not identify the additional feature or features relative to which the recited “pitches” are measured and further only identify the presence of singular “a gate electrodes” in each of the first and second die. Accordingly, this limitation in the claim is indefinite as it is unclear what constitutes “a minimum pitch of a gate electrode” and with respect to what feature the minimum pitch of a recited singular “a gate electrodes” is meant to be measured. Claim 20 recites the limitation “wherein a minimum pitch of a gate electrode of the first die is smaller than a minimum pitch of a gate electrode of each of the pair of second dies”. As understood in the art and as is consistent with the written description, “pitch” describes a spacing measurement between multiple objects or features. Claim 20 and parental claim 16, however, do not identify the additional feature or features relative to which the recited “pitches” are measured and further only identify the presence of singular “a gate electrodes” in each of the first and second dies. Accordingly, this limitation in the claim is indefinite as it is unclear what constitutes “a minimum pitch of a gate electrode” and with respect to what feature the minimum pitch of recited singular “a gate electrodes” is meant to be measured. Claims 4-6 depend from claim 3 and thus inherit the deficiencies identified supra . Claims 6 depends from claim 5 and thus inherits the deficiencies identified supra . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3-4, 7, and 9 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee (US 2020/0381393) . Regarding claim 1, Lee (see, e.g. , figs. 2-4, and 5 and pars.0023-0024, 0033/ll.9-11, 0052, 0054, 0057, and 0065) shows all aspects of the instant invention, including a memory device comprising: a base die structure BC/SOC including a first die BC and a second die SOC ; and a memory stack MC1/MC2/MC3 including memory dies MC1, MC2, MC3 sequentially stacked on the base die structure in a vertical direction D3 ; wherein: the first die BC is configured to be electrically connected to the memory stack MC1/MC2/MC3 (see, e.g. , par.0033/ll.9-11); and the first die includes a transistor TRT2 of a logic circuit, and the transistor of the logic circuit includes a channel of a three-dimensional structure Regarding claim 1, Lee (see, e.g. , Annotated Fig. 2 and figs. 2-4 and 5 and pars.0023-0024, 0033/ll.9-11, 0052, 0054, 0057, and 0065) shows all aspects of the instant invention, including a memory device comprising: a base die structure BC/SOC including a first die First Die and a second die (rightmost Second Die) ; and a memory stack MC1/MC2/MC3 including memory dies MC1, MC2, MC3 sequentially stacked on the base die structure in a vertical direction D3 ; wherein: the first die First Die is configured to be electrically connected to the memory stack MC1/MC2/MC3 (see, e.g. , par.0033/ll.9-11); and the first die includes a transistor TRT2 of a logic circuit, and the transistor of the logic circuit includes a channel of a three-dimensional structure Regarding claim 3, Lee (see paragraphs 16-17 above and, e.g. , Annotated Fig. 2 and figs. 2 and 5) shows that the memory stack MC1/MC2/MC3 includes through vias TV1 that are in the memory dies MC1, MC2, MC3 , wherein: each of the memory dies MC1, MC2, MC3 includes a through via region (portions of DP1 or dashed box around TV1 respectively corresponding to each of MC1, MC2, MC3 ) including terminals IM1, IM2, IM3 electrically connected to the through vias, respectively (see, e.g. , pars.0031-0035); and at least a portion of the first die BC or First Die overlaps a through via region (e.g., portion of DP1 or dashed box around TV1 respectively corresponding to MC3 ) in the vertical direction D3 With regards to other language recited in claim 3, see the comments stated above in paragraph 6. Regarding claim 4, Lee (see paragraphs 16-17 above and, e.g. , Annotated Fig. 2 and figs. 2 and 5) shows that a width of the first die BC or First Die is greater than a width of a through via region (portion of DP1 or dashed box around TV1 respectively corresponding to MC3 ) . With regards to other language recited in claim 4, see the comments stated above in paragraph 7. Regarding claim 7, Lee (see paragraphs 16-17 above and, e.g. , Annotated Fig. 2, and figs. 2 and 4-5 and pars.0023, 0054, 0057, and 0065) shows that the transistor TRT2 of the logic circuit includes a gate-all-around field-effect transistor (GAAFET). Regarding claim 9, Lee (see paragraph 16 above and, e.g. , figs. 2 and 4) shows that the first die BC includes a gate electrode GE and the second die SOC includes a gate electrode GE , wherein a minimum pitch between gate electrode portions PI2 of the first die is smaller than a minimum pitch between gate electrode portions ( e.g. , a pitch between leftmost CH2 and rightmost CH2 over NR in M ) of the second die (see, e.g. , par.0053/ll.9-11). With regards to other language recited in claim 9, see the comments stated above in paragraph 10 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Keeth (US 2021/0200464) . Regarding claim 16, Lee (see, e.g. , Annotated Fig. 2 and fig. 4 and pars.0023-0024, 0040, 0052, 0054, 0057, 0059-0060, 0065, and 0072) shows most aspects of the instant invention, including a semiconductor package comprising: a package substrate PSUB ; an interposer IPS on the package substrate; a logic die SOC on the interposer substrate and configured to generate a data signal; and a memory device on the interposer substrate and on a side of the logic die; wherein the memory device includes: a base die structure BC including a pair of second dies Second Die and a first die First Die between the pair of second dies; and a memory stack MC1/MC2/MC3 including memory dies MC1, MC2, MC3 sequentially stacked on the base die structure in a vertical direction D3 ; wherein: the first die First Die is configured to receive the data signal and a command address signal; and the first die includes a transistor TRT2 of a logic circuit, and the transistor of the logic circuit includes a channel of three-dimensional structure Lee shows most aspects of the instant invention, wherein Lee further teaches that the logic die is configured to transmit signals. Lee, however, fails to specify that the logic die is configured to generate a command address signal and that the first die is configured to receive this command address signal. Keeth, in the same field of endeavor and in a similar device to Lee, teaches a device 312 generating both a data signal and a command address signal, wherein such signals are sent 320 to a memory die stack 314 through a first die 300 (see, e.g. , Keeth: fig. 3 and pars.0033 and 0045-0046). Keeth teaches that the transmission of command/address signals can facilitate memory operations and data management and further teaches that such a transmission structure enables memory interfaces and associated interconnections to accommodate higher signal- and data-transfer demands and enables interconnection components, including TSVs, to better accommodate interactions supplied by the device while maintaining data and signal throughput (see, e.g. , Keeth: pars.0005 and 0038). Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lee’s logic die generate a data and a command address signal and to have Lee’s first die receive this data and command address signal, as taught by Keeth, so as to facilitate memory operations and data management and to expand the intercommunication capabilities and information transmission in Lee’s device while simultaneously enabling Lee’s memory interfaces and associated interconnections to accommodate higher data-transfer demands and while ensuring Lee’s interconnection components, taught to include TSVs, better accommodate interactions supplied by the device while maintaining data throughput. Regarding claim 17, Keeth (see, e.g. , fig. 3 and pars.0037-0045) shows that the first die 300 is configured to provide 320 data to the memory stack 314 based on the data signal 324 , and provide 320 a command/address to the memory stack based on the command address signal 322 . Regarding claim 18, Lee (see, e.g. , Annotated fig. 2 and figs. 4-5 and pars.0023 and 0065) shows that the transistor TRT2 of the logic circuit includes a gate-all-around field-effect transistor (GAAFET). Regarding claim 20, Lee (see e.g. , fig. 4 and pars.0043 and 0054) shows that the first die First Die includes a gate electrode GE and the second die Second Die includes a gate electrode GE , wherein a minimum pitch between gate electrode portions PI2 of the first die is smaller than a minimum pitch between gate electrode portions ( e.g. , a pitch between leftmost CH2 and rightmost CH2 over NR in N ) of the second die (see, e.g. , par.0053/ll.9-11). With regards to other language recited in claim 20, see the comments stated above in paragraph 11 . 07-21-aia AIA Claim s 2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Moon (US 2022/0310154) . Regarding claim 2, Lee shows most aspects of the instant invention (see paragraphs 16-17 above). Lee (see, e.g. , Annotated Fig. 2 and figs. 2 and 4-5) further shows that the first die BC or First Die includes a physical layer interface PHY2 connected to a through silicon via (TSV) circuit DP1 . Lee further teaches that TSVs are compatible with and integrated into Lee’s first die, and that communication between features of Lee’s device may be made through Lee’s first die (see, e.g. , Lee: figs. 2 and 4-5 and pars.0033-0035 and 0051/ll.12). Lee, however, fails to explicitly specify that Lee’s device includes a through silicon via (TSV) circuit. Moon, in the same field of endeavor and in a similar device to Lee, teaches a base die structure having a first die 310 having a TSV circuit 302 (see, e.g. , Moon: figs. 12 and 18). Moon teaches that the inclusion of such a TSV circuit in a first die facilitates communication and allows signals and/or data through the first die to be independently exchanged through corresponding TSVs, thereby enabling signals to be selectively routed to different locations within the device and in turn diversifying interconnect routing and improving communication flexibility (see, e.g. , Moon: pars.0129 and 0133). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a through silicon via (TSV) circuit in the first die of Lee, as taught by Moon, in order to facilitate communication and allow signals and/or data to be independently and selectively exchanged through corresponding TSVs, thereby diversifying interconnect routing and improving communication flexibility in Lee’s device. Regarding claim 5, Lee shows most aspects of the instant invention (see paragraphs 16-18 above). Lee (see, e.g. , Annotated Fig. 2 and figs. 2 and 5 and par.0028) further shows that each of the memory dies MC1, MC2, MC3 includes a first region (region of each of MC1, MC2, MC3 to the left of DP1 , extending to and including SW1 ) and a second region (region of each of MC1, MC2, MC3 to the right of DP3 , extending to and including SW2 ) , the first and second regions including memory areas, and wherein a through via region (portion of DP1 or dashed box around TV1 respectively corresponding to MC3 ) is between the first region and the second region. Lee teaches that the first region and second region may include memory features (see, e.g. , par.0028). Lee, however, fails to specify that the first region and second region are a first cell region and a second cell region, and that the first and second cell regions include memory cell areas. Moon, in the same field of endeavor and in a similar device to Lee, teaches a device having multiple stacked memory dies 320, 330, 340 350 , wherein each of the memory dies includes a first cell region (region including Bank0, Bank1, Bank2, Bank3 below TSV area ) and a second cell region (region including Bank4, Bank5, Bank6, Bank7 above TSV area ) , wherein the first and second cell regions include memory cell areas Bank0, Bank1, Bank2, Bank3, Bank4, Bank5, Bank6, Bank7 , and wherein a through via region TSV area is between each of the first cell regions and second cell regions (see, e.g. , Moon: figs. 12 and 18 and par.0127). Moon teaches that the inclusion of such memory cell regions and memory cell areas facilitates the storage and output of data, wherein Moon additionally teaches that the memory cell areas may further be connected with other components, such as word lines and bit lines, a row decoder, a column decoder, and a sense amplifier, thereby facilitating access to and management of data stored within the memory cell regions (see, e.g. , Moon: par.0034/ll.14-15, 0127, and 0144). Moon further teaches that the memory cell areas may allow for signals and/or data to be independently exchanged to specific regions of each memory die, thereby enabling signals to be selectively routed to different locations within the device, and in turn diversifying interconnect routing and improving communication flexibility while simultaneously facilitating intercommunication between dies of the device (see, e.g. , Moon: pars.0129 and 0133). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lee’s first and second regions be first and second cell regions, respectively, and to have the first and second cell regions include memory cell areas, as taught by Moon, so as to facilitate the access to and storage, management, and output of data while simultaneously allowing signals and/or data to be independently and selectively exchanged to specific regions of each memory die, thereby diversifying interconnect routing and improving communication flexibility while facilitating intercommunication between dies in Lee’s device. With regards to other language recited in claim 5, see the comments stated above in paragraph 8. Regarding claim 6, Lee (see paragraph 16 and 18 above and, e.g. , figs. 2 and 5) shows that a first side surface of the first die BC overlaps a first cell region (region of MC3 to the left of DP1 , extending to and including SW1 ) in the vertical direction D3 , and wherein a second side surface of the first die, which is opposite the first side surface of the first die, overlaps a second cell region (region of MC3 to the right of DP3 , extending to and including SW2 ) in the vertical direction. See the comments stated above in paragraphs 37-40 regarding the first and second cell regions, which are considered to be repeated here. Furthermore, Moon (see, e.g. , figs. 12 and 18) shows that a first side surface of the first die 310 overlaps a first cell region (region including Bank0, Bank1, Bank2, Bank3 below TSV area in 310 ) in a vertical direction, and wherein a second side surface of the first die, which is opposite to the first side surface of the first die, overlaps a second cell region (region including Bank4, Bank5, Bank6, Bank7 above TSV area in 310 ) in the vertical direction. With regards to other language recited in claim 6, see the comments stated above in paragraph 9 . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Gomes (US 2022/0173090) . Regarding claim 8, Lee shows most aspects of the instant invention (see paragraphs 16 and 22 above). Lee (see, e.g. , figs. 2 and 4 and pars.0023/ll.1-2 and 0057) further shows that the second die SOC includes a transistor TRT1 of a circuit ACL1 including a gate electrode GE . However, the active layer ACL1 of the second die does not explicitly disclose a memory circuit. Lee nevertheless teaches such a feature in Lee’s first die. Specifically, Lee discloses that the first die may comprise a combination of a memory and a logic circuit, wherein Lee further describes the active layers of the first die and the second die to be nearly structurally identical (see, e.g. , fig. 4). It would have been obvious to one of ordinary skill in the art at the time of filing the invention to have Lee’s second die include a memory circuit and memory transistor as taught in Lee’s first die. Doing so would have been motivated by the fact that Lee acknowledges such features as valid and compatible with Lee’s dies, alongside efficiency improvements and reducing form factor. Lee, however, fails to specify that the transistor includes a planar gate electrode. Gomes, in the same field of endeavor and in a similar device to Lee teaches gate electrodes to be integral for inducing conductive channels, and further teaches planar gate electrodes to be functionally equivalent to non-planar gate electrodes in memory devices (see, e.g. , Gomes: fig. 1 and pars.0081, 0091, and 0163-0165). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lee’s transistor of a memory circuit include a gate electrode, as taught by Gomes, so as to include an integral component for inducing conductive channels in Lee’s transistor. Furthermore, Gomes is evidence showing that one of ordinary skill in the art would appreciate that a planar gate electrode would be equivalent to a non-planar gate electrode, and that such differences would result in no unexpected changes in the performance of the device of Lee. That is, both gate electrode structures would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a planar gate electrode, as taught by Gomes, or a non-planar gate electrode, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Regarding claim 8, Lee shows most aspects of the instant invention (see paragraphs 17 and 22 above). Lee (see, e.g. , Annotated Fig. 2 and fig. 4 and pars.0023/ll.1-2, 0028, and 0057) further shows that the second die Second Die includes a transistor of a memory circuit. Lee, however, fails to specify that the transistor includes a planar gate electrode. Gomes, in the same field of endeavor and in a similar device to Lee teaches gate electrodes to be integral for inducing conductive channels, and further teaches planar gate electrodes to be functionally equivalent to non-planar gate electrodes in memory devices (see, e.g. , Gomes: fig. 1 and pars.0081, 0091, and 0163-0165). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lee’s transistor of a memory circuit include a gate electrode, as taught by Gomes, so as to include an integral component for inducing conductive channels in Lee’s transistor. Furthermore, Gomes is evidence showing that one of ordinary skill in the art would appreciate that a planar gate electrode would be equivalent to a non-planar gate electrode, and that such differences would result in no unexpected changes in the performance of the device of Lee. That is, both gate electrode structures would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a planar gate electrode, as taught by Gomes, or a non-planar gate electrode, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007) . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee/Keeth in view of Gomes . Regarding claim 19, Lee/Keeth shows most aspects of the instant invention (see paragraphs 27-30 above). Lee (see, e.g. , Annotated Fig. 2 and fig. 4 and pars.0023/ll.1-2, 0028, and 0057) further shows that each of the pair of second dies Second Die includes a transistor of a memory circuit. Lee, however, fails to specify that the transistor includes a planar gate electrode. Gomes, in the same field of endeavor and in a similar device to Lee teaches gate electrodes to be integral for inducing conductive channels, and further teaches planar gate electrodes to be functionally equivalent to non-planar gate electrodes in memory devices (see, e.g. , Gomes: fig. 1 and pars.0081, 0091, and 0163-0165). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Lee’s pair of second dies’ transistors of a memory circuit include a gate electrode, as taught by Gomes, so as to include an integral component for inducing conductive channels in Lee’s transistor. Furthermore, Gomes is evidence showing that one of ordinary skill in the art would appreciate that a planar gate electrode would be equivalent to a non-planar gate electrode, and that such differences would result in no unexpected changes in the performance of the device of Lee. That is, both gate electrode structures would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a planar gate electrode, as taught by Gomes, or a non-planar gate electrode, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable conductive gate structures capable of regulating current inside a transistor channel. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300 . The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Shamita S. Hanumasagar/ Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 2 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 3 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 4 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 5 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 6 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 7 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 8 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 9 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 10 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 11 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 12 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 13 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 14 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 15 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 16 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 17 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 18 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 19 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 20 Art Unit: 2814 Application/Control Number: 18/452,616 (Non-Final Rejection) Page 21 Art Unit: 2814
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