Prosecution Insights
Last updated: April 19, 2026
Application No. 18/452,737

THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE CONTACT LAYER HAVING HORIZONTALLY AND VERTICALLY EXTENDING PORTIONS AND METHODS OF FORMING THE SAME

Non-Final OA §112
Filed
Aug 21, 2023
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Western Digital Technologies Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
532 granted / 723 resolved
+5.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 723 resolved cases

Office Action

§112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Regarding Claim 1, the limitation “wherein the source contact layer comprises a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and contacting a bottommost insulating layer within the alternating stack” is open to multiple interpretations, such as: “wherein the source contact layer comprises a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, the vertical portion having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and the vertical portion contacting a bottommost insulating layer within the alternating stack” or: “wherein the source contact layer comprises a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, the source contact layer having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and the source contact layer contacting a bottommost insulating layer within the alternating stack.” The multiple reasonable interpretations render the claim indefinite. Based on the description, drawings, and the further limitation of Claim 2, the former interpretation is assumed for examination purposes. Allowable Subject Matter Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 1, U.S. Pat. No. 9824966 to Kanakamedala et al. teaches in Fig. 18 at least, memory device, comprising: source-level material layers including a source-level semiconductor layer 61, a source contact layer 146; an alternating stack of insulating layers 32 and electrically conductive layers 46 located over the source-level material layers; a memory opening vertically extending through the alternating stack and into an upper portion of the source-level material layers; and a memory opening fill structure located in the memory opening and comprising a memory film 50 and a vertical semiconductor channel 60, wherein the source contact layer comprises a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion (sideways T shape of 146), and contacting a bottommost insulating layer within the alternating stack (146 and lowermost 32 are in contact, see Fig. 18). Kanakamedala does not teach a lower and upper source layer, or the source contact having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel. In analogous art, U.S. Pat. No. 10916556 to Sakakibara et al. teaches in Fig. 18B at least, a source contact layer 114 having a vertical 114C and horizontal 114A portion in between a lower source-level semiconductor layer 112 and an upper source-level semiconductor layer 116. Furthermore, the inner sidewall of the vertical portion 114C of the source contact directly contacts the channel 60. It would have been obvious to the person of ordinary skill in the art before the time of filing to rearrange the single source layer 61 of Kanakamedala to the upper and lower source-level layers of Sakakibara to benefit from a greater contact area between the source contact and the source layer, decreasing resistance and increasing efficiency, as shown by Sakakibara in Fig. 28 and the associated text. However, neither Kanakamedala nor Sakakibara teach that the vertical portion contacting a bottommost insulating layer. Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, as Claim 2 alleviates the indefiniteness of Claim 1. Claims 7-12 are rejected as being dependent on an indefinite base claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 21, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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PROBE CARD CONFIGURED TO CONNECT TO A PROBE PAD LOCATED IN SAW STREET OF A SEMICONDUCTOR WAFER
2y 5m to grant Granted Apr 14, 2026
Patent 12598748
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12598701
SEMICONDUCTOR DEVICE WITH SELECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12586736
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2y 5m to grant Granted Mar 24, 2026
Patent 12588324
PACKAGE STRUCTURE AND FORMING METHOD THEREOF
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 723 resolved cases by this examiner. Grant probability derived from career allow rate.

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