DETAILED ACTION
This correspondence is in response to the communications received 01/26/2026. Claims 1-11 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 01/26/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/21/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a method of manufacturing a semiconductor device (CP) comprising steps of:
(a) preparing a semiconductor substrate (SB) including a plurality of chip formation regions (CR) and a scribe region (SR) positioned between two chip formation regions of the plurality of chip formation regions, the two chip formation regions being adjacent to each other (see Fig. 7);
(b) after the step (a), forming a semiconductor element (the semiconductor element is not shown, however it is formed in "the element region DR") in each of the plurality of chip formation regions, and forming a dummy semiconductor element (the dummy semiconductor element is not shown, however it is formed in "the test element region TS") in the scribe region;
(c) after the step (b), inspecting the dummy semiconductor element by using a metal pattern ("testing electrode (metal pattern) TE") which is provided in the scribe region and which is electrically connected to the dummy semiconductor element; and
(d) after the step (c), cutting the scribe region of the semiconductor substrate by using a dicing blade,
wherein the metal pattern includes:
a plurality of inspecting pad portions (PD); and
a plurality of connection portions (CN) respectively provided between the plurality of inspecting pad portions, each of the plurality of connection portions connecting two inspecting pad portions of the plurality of inspecting pad portions to each other, the two inspecting pad portions being adjacent to each other (see Fig. 18),
wherein, in plan view, a width of each of the plurality of connection portions (W2) is larger than a width of the dicing blade (W3), and smaller than a width of each of the plurality of inspecting pad portions (W1), and
wherein, in plan view, the plurality of inspecting pad portions is arranged in a linear manner in a moving direction of the dicing blade, while the plurality of connection portions is arranged in a staggered manner in the moving direction of the dicing blade (see Fig. 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kozaki (US 8,492,763 B2, published 07/23/2013) in view of Eguchi et al. (US 10,026,663 B2, published 07/17/2018).
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Regarding claim 1, Figs. 1A-4 of Kozaki disclose a method of manufacturing a semiconductor device (see title) comprising steps of:
(a) preparing a semiconductor substrate (“a semiconductor substrate 10i to be used for formation of a plurality of semiconductor devices 100 and 100a (see FIG. 3C) is prepared”, col. 5, lines 19-21) including a plurality of chip formation regions (“a predetermined circuitry device is formed on each of a plurality of chip areas 11 and 11a corresponding to the plurality of semiconductor devices 100 and 100a”, col. 5, lines 24-26) and a scribe region (the area between 11a and 11 as seen in Fig. 2B is a scribe region that contains “scribe lines SL”, col. 5, line 25, where SL is the area that will be removed during the forthcoming dicing process) positioned between two chip formation regions of the plurality of chip formation regions (“In the semiconductor substrate 10i, scribe lines SL extend, in a lattice form, between the plurality of chip areas 11 and 11a (to demarcate the plurality of chip areas 11 and 11a)”, col. 5, lines 34-37), the two chip formation regions being adjacent to each other (as seen in Fig. 2B, 11 and 11a are adjacent to each other);
(b) after the step (a), forming a semiconductor element in each of the plurality of chip formation regions (“In a process illustrated in FIG. 2B, a predetermined circuitry device is formed on each of a plurality of chip areas 11 and 11a corresponding to the plurality of semiconductor devices 100 and 100a”, col. 5, lines 24-27), and forming a dummy semiconductor element in the scribe region (“In a process illustrated in FIG. 2C, a plurality of TEGs 51 and 52 and a plurality of inspection pads 31i to 34i (see FIG. 4) are formed on the scribe line SL of the semiconductor substrate 10i”, col. 5, lines 38-41, where TEG is a “test element group” “including an element such as a resistive element, a contact element, and a transistor”, col. 1, lines 22-23, 51 and 52 are test elements that will be removed during a later cutting process, thus as per page 23, lines 3-7 of the instant specification 51 and 52 are dummy semiconductor elements. Further, in order to form the predetermined circuitry in 11 and 11a and form 51 and 52 in SL, both of which are on 10i, the formation of the predetermined circuity, 51, and 52 must necessarily have occurred after the preparation of 10i);
(c) after the step (b), inspecting the dummy semiconductor element by using a metal pattern which is provided in the scribe region (31i-34i are interpreted as a metal pattern as “patterning of the inspection pads 31i to 34i and the edge seals 20 (20L) and 20a (20Ra) is performed. For example, the inspection pads 31i to 34i and the edge seals 20 and 20a are formed of metal such as aluminum”, col. 5, lines 51-55, in addition, the wiring between 31i-34i, and 51 and 52 are considered part of the metal pattern, and as seen in Fig. 4, 31i-34i are in the region between 11 and 11a. Further, “In a process illustrated in FIG. 3B, the tips of inspection probes 61 to 64 are brought into contact with the inspection pads 31i to 34i in a direction intersecting the portions 20L and 20Ra of the edge seal 20 and the insulating film patterns 40 and 40a, and then an inspection of the TEGs 51 and 52 is performed” col. 6, lines 24-29, inspection of 51 and 52 must necessarily occur after the formation of 51 and 52) and which is electrically connected to the dummy semiconductor element (as seen in Fig. 4, 31i and 32i are connected to 51, and 33i and 34i are connected to 52, further, “Predetermined signals are supplied from the inspection pads 31i and 32i to inspect the TEG 51, and predetermined signals are supplied from the inspection pads 33i and 34i to inspect the TEG 52”, col. 6, lines 29-32, thus 31i and 32i are electrically connected to 51, and 33i and 34i are electrically connected to 52); and
(d) after the step (c), cutting the scribe region of the semiconductor substrate (“In a process illustrated in FIG. 3C, the semiconductor substrate 10i is cut along the scribe line SL (see FIG. 4), and the semiconductor substrate is divided into the plurality of semiconductor devices 100 and 100a”, col. 6, lines 33-36) by using a dicing blade (Kozaki does not specify using a dicing blade, however, a secondary reference will be utilized to teach this limitation below),
wherein the metal pattern includes:
a plurality of inspecting pad portions (“plurality of inspection pads 31i to 34i”, col. 5, line 39); and
a plurality of connection portions (“W1 and W2”, denoted in Fig. 4, connect 31i-34i to 51 and 52, W1 and W2 are further split into a and b portions for ease of reference) respectively provided between the plurality of inspecting pad portions (as seen in Fig. 4, W1 is between 31i and 32i, and W2 is between 33i and 34i), each of the plurality of connection portions connecting two inspecting pad portions of the plurality of inspecting pad portions to each other (as seen in Fig. 4, W1 connects 31i and 32i, and W2 connects 33i and 34i), the two inspecting pad portions being adjacent to each other (as seen in Fig. 4, 31i and 32i are adjacent to each other, and 33i and 34i are adjacent to each other),
Kozaki fails to disclose “cutting the scribe region of the semiconductor substrate by using a dicing blade”.
However, in a similar field of endeavor, Figs. 1-4 of Eguchi teach cutting the scribe region of the semiconductor substrate by using a dicing blade (“the center of the dicing line 20 constitutes a cut region 20a cut actually by the dicing blade 30”, col. 5, lines 57-59, where 201 of Eguchi is equivalent to SL of Kozaki).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “cutting the scribe region of the semiconductor substrate by using a dicing blade” as taught by Eguchi in the system of Kozaki for the purpose of demonstrating a specific technique for cutting a semiconductor technique.
Figs. 1A-4 of Kozaki further disclose wherein, in plan view (Fig. 4 is plan view), a width of each of the plurality of connection portions is larger than a width of the dicing blade (as seen in Fig. 4, the widths of W1 and of W2 are larger than the width of SL which is equivalent to the width of 30 of Eguchi), and smaller than a width of each of the plurality of inspecting pad portions blade (as seen in Fig. 4, the widths of W1 and of W2 are smaller than the widths of 31i-34i), and
wherein, in plan view, the plurality of inspecting pad portions is arranged in a linear manner in a moving direction of the dicing blade (as seen in Fig. 4, 31i-34i are arranged in a linear manner in the vertical direction, where one having ordinary skill in the art would understand that the vertical direction of Fig. 4 would be a moving direction of 30 of Eguchi after modifying Kozaki with Eguchi), while the plurality of connection portions is arranged in a staggered manner in the moving direction of the dicing blade (as seen in Fig. 4, W1 and W2 are arranged in a staggered manner in the vertical direction, as W1a and W2a both extend towards the top of Fig. 4, and W1b and W2b both extend towards the bottom of Fig. 4).
Allowable Subject Matter
Claim 11 is allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the method of manufacturing a semiconductor device as recited in the claims of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 11, the prior art of Kozaki (US 8,492,763 B2) in combination with Eguchi et al. (US 10,026,663 B2) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the metal pattern, specifically the arrangement of the first and second connection portions relative to the inspecting pad portions and the dicing blade e.g.
“wherein each of the plurality of connection portions includes a first side extending in a moving direction of the dicing blade, and a second side extending in the moving direction of the dicing blade and positioned on an opposite side to the first side in a first direction intersecting the moving direction,
wherein the plurality of connection portions is formed of a first connection portion and a second connection portion which are alternately arranged via each of the inspecting pad portions,
wherein, in plan view, the plurality of inspecting pad portions is arranged in a linear manner in the moving direction of the dicing blade, and
wherein, in the step (d), each of the second side of the first connection portion and the first side of the second connection portion is included in a cutting region cut by the dicing blade, but each of the first side of the first connection portion and the second side of the second connection portion is not included in the cutting region.”
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the method of manufacturing a semiconductor device as recited in the claims of the instant application.
Regarding claim 2, the prior art of Kozaki (US 8,492,763 B2) in combination with Eguchi et al. (US 10,026,663 B2) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the metal pattern, specifically the arrangement of the first and second connection portions relative to the inspecting pad portions and the dicing blade e.g.
“wherein each of the plurality of connection portions has a first side and a second side which extend in the moving direction of the dicing blade and are positioned on opposite sides to each other in a first direction intersecting the moving direction of the dicing blade,
wherein the plurality of connection portions is formed of first connection portions and second connection portions which are alternately arranged with the respective inspecting pad portions interposed therebetween,
wherein the first side of the first connection portion is not included in a cutting region cut by the dicing blade in the step (d), but the second side of the first connection portion is included in the cutting region, and
wherein the first side of the second connection portion is included in the cutting region, but the second side of the second connection portion is not included in the cutting region.”
Claims 3-10 are allowable by virtue of their dependence on claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893