Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant elected Group I, claims 1-15, without traverse. Currently, claims 1-15 are pending, and claims 16-20 have been withdrawn from further consideration.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Currently, the title has been changed to:
“SEMICONDUCTOR DEVICE USED IN AN OSCILLATION CIRCUIT”
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsao et al. (Pub. No. US 2012/0319210 A1, herein Tsao).
Regarding claim 1, Tsao discloses a semiconductor device including an oscillation circuit (Tsao: paragraph [0003]), comprising: a semiconductor substrate; a plurality of first MISFETs 198/200 formed on the semiconductor substrate; and a plurality of second MISFETs 196 formed on the semiconductor substrate, wherein each of the plurality of first MISFETs includes: a first semiconductor region 188 formed in the semiconductor substrate and acting as a source or a drain (Tsao: Fig. 1M and paragraph [0026]; n-type low-noise NMOS NSD regions 188); a first gate electrode 198 formed on the semiconductor substrate via a first gate dielectric film 126 (Tsao: Fig. 1M and paragraphs [0014], [0028]); and a first halo region 168 of a conductivity type opposite to a conductivity type of the first semiconductor region, the first halo region formed in the semiconductor substrate so as to be adjacent to the first semiconductor region (Tsao: Fig. 1M and paragraph [0023]; p-type low-noise NMOS halo regions 168), wherein each of the plurality of second MISFETs includes: a second semiconductor region 186 formed in the semiconductor substrate and acting as a source or a drain (Tsao: Fig. 1M and paragraph [0026]; n-type logic NMOS NSD regions 186); and a second gate electrode 196 formed on the semiconductor substrate via a second gate dielectric film 126 (Tsao: Fig. 1M and paragraph [0028]), wherein the each of the plurality of second MISFETs does not include a halo region of the conductivity type opposite to the conductivity type of the first semiconductor region in a position adjacent to the second semiconductor region in the semiconductor substrate (Tsao: Fig. 1M and paragraph [0022]; n-type logic NMOS NMDD regions 152), and wherein the plurality of second MISFETs is used as a pair transistor included in the oscillation circuit (Tsao: Fig. 1M and paragraph [0009]).
Regarding claim 2, Tsao discloses the semiconductor device according to claim 1, comprising: a logic circuit, wherein the plurality of first MISFETs is used as the logic circuit (Tsao: Fig. 1M and paragraphs [0007]-[0009]).
Regarding claim 3, Tsao discloses the semiconductor device according to claim 1, wherein the plurality of first MISFETs is used as a MISFET other than the pair transistor included in the oscillation circuit (Tsao: Fig. 1M and paragraphs [0007]-[0009]).
Regarding claim 4, Tsao discloses the semiconductor device according to claim 1, comprising: a memory circuit, wherein the plurality of first MISFETs is used as the memory circuit (Tsao: Fig. 1M and paragraphs [0003], [0007]-[0009]).
Regarding claim 5, Tsao discloses the semiconductor device according to claim 1, comprising: a logic circuit; and a memory circuit, wherein the plurality of first MISFETs is used as a MISFET other than the pair transistor included in the oscillation circuit, the logic circuit, and the memory circuit (Tsao: Fig. 1M and paragraphs [0003], [0007]-[0009]).
Regarding claim 6, Tsao discloses the semiconductor device according to claim 1, wherein the first gate dielectric film included in the each of the plurality of first MISFETs has the same thickness as a thickness of the second gate dielectric film included in the plurality of second MISFETs (Tsao: Fig. 1M and paragraphs [0002]-[0003], [0007]-[0009]).
Regarding claim 8, Tsao discloses a semiconductor device including an oscillation circuit (Tsao: paragraph [0003]), comprising: a semiconductor substrate; and a first MISFET 198/200 used as a pair transistor included in the oscillation circuit; and a second MISFET 196 used as the pair transistor included in the oscillation circuit, wherein the first MISFET includes: a first semiconductor region 188 of a first conductivity type formed in the semiconductor substrate and acting as a source or a drain (Tsao: Fig. 1M and paragraph [0026]; n-type low-noise NMOS NSD regions 188); and at least one first gate electrode 198 formed on the semiconductor substrate via a first gate dielectric film 126 (Tsao: Fig. 1M and paragraphs [0014], [0028]), wherein the second MISFET includes: a second semiconductor region 186 of the first conductivity type formed in the semiconductor substrate and acting as a source or a drain (Tsao: Fig. 1M and paragraph [0026]; n-type logic NMOS NSD regions 186); and a second gate electrode 196 formed on the semiconductor substrate via a second gate dielectric film 126 (Tsao: Fig. 1M and paragraph [0028]), wherein the first MISFET does not include a halo region of a second conductivity type opposite to the first conductivity type in a position adjacent to the first semiconductor region in the semiconductor substrate (Tsao: Fig. 1M and paragraph [0023]; n-type low-noise NMOS NMDD regions 164), wherein the second MISFET does not include a halo region of the second conductivity type in a position adjacent to the second semiconductor region in the semiconductor substrate (Tsao: Fig. 1M and paragraph [0022]; n-type logic NMOS NMDD regions 152), and wherein the at least one first gate electrode and the second gate electrode are electrically connected to each other (Tsao inherently discloses this limitations as the gate electrodes are connected to each other via a word line.).
Regarding claim 9, Tsao discloses the semiconductor device according to claim 8, comprising: a third MISFET 200 used as a logic circuit, wherein the third MISFET includes: a third semiconductor region 178 of the first conductivity type formed in the semiconductor substrate and acting as a source or a drain (Tsao: Fig. 1M and paragraph [0024]); a third gate electrode 200 formed on the semiconductor substrate via a third gate dielectric film 126 (Tsao: Fig. 1M and paragraph [0028]), and a first halo region 176 of the second conductivity type formed in the semiconductor substrate so as to be adjacent to the third semiconductor region, wherein a thickness of the first gate dielectric film, a thickness of the second gate dielectric film, and a thickness of the third gate dielectric film are the same as each other (Tsao: Fig. 1M and paragraph [0024]).
Regarding claim 10, Tsao discloses the semiconductor device according to claim 8, comprising: an element isolation region 110 formed in the semiconductor substrate, wherein the first semiconductor region is formed in a first active region surrounded by the element isolation region in the semiconductor substrate, wherein the second semiconductor region is formed in a second active region surrounded by the element isolation region in the semiconductor substrate, wherein the at least one first gate electrode extends so as to be across the first active region in plan view, and wherein the second gate electrode extends so as to be across the second active region in plan view (Tsao: Fig. 1M and paragraphs [0010], [0019]).
Regarding claim 11, Tsao inherently discloses the semiconductor device according to claim 10, wherein a direction of current flowing in the semiconductor substrate by the first MISFET is the same as a direction of current flowing in the semiconductor substrate by the second MISFET (Tsao: Fig. 1M and paragraph [0023]).
Regarding claim 12, Tsao inherently discloses the semiconductor device according to claim 10, wherein a first conductor portion extending on the semiconductor substrate so as to be along an outer periphery of the first active region is integrally formed with the first gate electrode (Tsao: Fig. 1M and paragraph [0003]; Tsao does not specifically show the conductors/conductive vias. However, it is inherent to the semiconductor MISFETs/MOSFETs and integrated circuits to have conductor vias/plugs for gate electrodes and source/drain regions, where each group of conductors are connected to each other and form bit lines and word lines.).
Regarding claim 13, Tsao inherently discloses the semiconductor device according to claim 10, wherein the at least one first gate electrode includes a plurality of first gate electrodes, and wherein the plurality of first gate electrodes is electrically connected to each other (Tsao: Fig. 1M and paragraph [0003]; Tsao does not specifically show the conductors/conductive vias. However, it is inherent to the semiconductor MISFETs/MOSFETs and integrated circuits to have conductor vias/plugs for gate electrodes and source/drain regions, where each group of conductors are connected to each other and form bit lines and word lines.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Luan (Pub. No. US 2017/0053927 A1).
Regarding claim 14, Tsao does not specifically show the first, second and third directions in the top view.
However, in the same field of endeavor, Luan teaches the semiconductor device according to claim 13, wherein each of the plurality of first gate electrodes extends “WL” in a first direction and arranged in a second direction orthogonal to the first direction, wherein a plurality of first distances between the plurality of first gate electrodes is the same as each other (Luan: Figs. 6, 9, 11, 13, 15 and paragraphs [0028], [0030]), wherein a second distance between the element isolation region and one of two, among the plurality of first gate electrodes arranged in the second direction, located at both ends in the second direction is greater than each of the plurality of first distances, and wherein a third direction between the element isolation region and another one of the two, among the plurality of first gate electrodes arranged in the second direction, located at the both ends in the second direction is greater than the each of the plurality of first distances (The limitations of this claim are broad and the distances can be taken to be any distance between two adjacent, every other strips or even farther distances with respect to other strips of WL, BL or Isolation.) to obtain cross-point memory arrays that are advantageous due to its compact layout and simple decoding while avoiding significant process complexity and array leakage current (Luan: paragraph [0006]).
Therefore, given the teachings of Luan, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Tsao in view of Luan by employing the claimed distances.
Allowable Subject Matter
Claims 7 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein the first semiconductor region includes: a first low concentration region; and a first high concentration region having the same conductivity type as a conductivity type of the first low concentration region and having an impurity concentration higher than an impurity concentration of the first low concentration region, wherein the second semiconductor region includes: a second low concentration region; and a second high concentration region having the same conductivity type as a conductivity type of the second low concentration region and having an impurity concentration higher than an impurity concentration of the second low concentration region, and wherein the first halo region is formed in a position adjacent to the first low concentration region.
Regarding claim 15, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, wherein each of the plurality of first gate electrodes extends in a first direction and arranged in a second direction orthogonal to the first direction, wherein a first dummy electrode extending in the first direction is disposed between the element isolation region and one of two, among the plurality of first gate electrodes arranged in the second direction, located at both ends in the second direction, and wherein a second dummy electrode extending in the first direction is disposed between the element isolation region and another one of the two, among the plurality of first gate electrodes arranged in the second direction, located at the both ends in the second direction.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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April 1, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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