Prosecution Insights
Last updated: July 17, 2026
Application No. 18/452,845

COMMON LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR FORMING A COMMON LEAD FRAME, AND CONTROL PROGRAM

Non-Final OA §102§103§112
Filed
Aug 21, 2023
Priority
Oct 20, 2022 — JP 2022-168097
Examiner
CRITE, ANTONIO B
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
366 granted / 451 resolved
+13.2% vs TC avg
Minimal -13% lift
Without
With
+-13.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
476
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.7%
+36.7% vs TC avg
§102
12.6%
-27.4% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 451 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Action is responsive to the communication filed on 08/21/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 4-6, 9-10, and 13-14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Claim 4, which depends from Claim 1, recites the limitation: “the common lead frame can be used for any of the first package, the second package, and a third package” (emphasis added). However, Claim 1 recites the limitation: “a common lead frame can be used for both a first package and a second package” (emphasis added). The metes and bounds of the claimed invention are unclear because Claim 4 recites that the common lead can be used for any first, second, or third packages. Yet, Claim 1 recites that the common lead can be used for both the first and second packages. Therefore, Claim 4 has been rendered indefinite. Claims 5-6 are rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 4. Claim 9, which depends from Claim 7, recites the limitation: “a common lead frame can be used for any of the first package, the second package, and a third package” (emphasis added). However, Claim 7 recites the limitation: “a common lead frame can be used for both a first package and a second package” (emphasis added). The metes and bounds of the claimed invention are unclear because Claim 9 recites that the common lead can be used for any first, second, or third packages. Yet, Claim 7 recites that the common lead can be used for both the first and second packages. Therefore, Claim 9 has been rendered indefinite. Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 9. Claim 9, which depends from Claim 7, recites the limitation: “a common lead frame can be used for any of the first package, the second package, and a third package” (emphasis added). However, Claim 7 recites the limitation: “a common lead frame can be used for both a first package and a second package” (emphasis added). It is unclear whether the common lead frame recited in Claim 9 refers back to the common lead frame recited in Claim 7, or introduces another common lead frame into the claimed invention. Therefore, Claim 9 has been rendered indefinite. Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 9. Claim 13, which depends from Claim 11, recites the limitation: “the common lead frame can be used for any of the first package, the second package, and a third package” (emphasis added). However, Claim 11 recites the limitation: “a common lead frame can be used for both a first package and a second package” (emphasis added). The metes and bounds of the claimed invention are unclear because Claim 13 recites that the common lead can be used for any first, second, or third packages. Yet, Claim 11 recites that the common lead can be used for both the first and second packages. Therefore, Claim 13 has been rendered indefinite. Claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 13. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masao (JP 2019 041062 A). Regarding claim 1, Masao (see, e.g., FIG. 2, FIG. 6) discloses a common lead frame that can be used for both a first package and a second package, the common lead frame having: a planar shape according to specifications of each of a first chip 21, on lower left die pad 11 used in the first package 20, for lower left package region 10a and a second chip 21, on middle left die pad 11 used in the second package 20, for middle left package region 10a (Para 0021, Para 0023), wherein a thickness of at least a part of a lead portion 12, outer portion (see FIG. 6) through which any one of a first cutting line C1, e.g., upper side of lower left package region 10a corresponding to an outer peripheral side e.g., upper side of lower left package region 10a of the first package 20, for lower left package region 10a and a second cutting line C1, e.g., upper side of middle left package region 10a corresponding to an outer peripheral side e.g., upper side of middle left package region 10a of the second package 20, for middle left package region 10a passes is smaller than a thickness of a lead portion 12 through which the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a do not pass (Para 0035, Para 0045). Regarding claim 2, Masao (see, e.g., FIG. 2, FIG. 6) teaches the common lead frame according to claim 1, wherein a through hole e.g., space created by cutting area 46 is formed in at least a part of a lead portion 12 through which any one of the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a passes (Para 0021). Regarding claim 3, Masao (see, e.g., FIG. 2, FIG. 6) teaches a semiconductor device 20 that is either the first package 20, for lower left package region 10a or the second package 20, for middle left package region 10a for which the common lead frame according to claim 1 is used. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Masao (JP 2019 041062 A), and further in view of Kierse (US 2014/0035113). Regarding claim 7, Masao (see, e.g., FIG. 2, FIG. 6) discloses a method for forming a common lead frame, the method comprising: form a planar shape of a common lead frame 10 that can be used for both a first package 20, for lower left package region 10a and a second package 20, for middle left package region 10a, based on specifications of each of a first chip 21, on lower left die pad 11 used in the first package 20, for lower left package region 10a and a second chip 21, on middle left die pad 11 used in the second package 20, for middle left package region 10a (Para 0021, Para 0023); and make a thickness of at least a part of a lead portion 12, outer portion (see FIG. 6) through which any one of a first cutting line C1, e.g., upper side of lower left package region 10a corresponding to an outer peripheral side e.g., upper side of lower left package region 10a of the first package 20, for lower left package region 10a and a second cutting line C1, e.g., upper side of middle left package region 10a corresponding to an outer peripheral side e.g., upper side of middle left package region 10a of the second package 20, for middle left package region 10a passes smaller than a thickness of a lead portion 12 through which the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a do not pass in the common lead frame 10 (Para 0035, Para 0045). Although the method as disclosed by Masao shows substantial features of the claimed invention, Masao fails to expressly teach a computer performing the method. Kierse (see, e.g., FIG. 2A – FIG. 2L) teaches a computer e.g., dry or wet etching system for the purpose of producing a plurality of smooth recessed region in a lead frame (Para 0050-Para 0054). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a common lead frame that can be used for both a first package and a second package and making a portion of a lead portion smaller of Masao to include a computer as described by Kierse for the purpose of producing a plurality of smooth recessed regions in a lead frame (Para 0054). Regarding claim 8, Masao (see, e.g., FIG. 2, FIG. 6) teaches the method for forming a common lead frame according to claim 7, the method comprising: forming a through hole e.g., space created by cutting area 46 in at least a part of a lead portion 12 through which any one of the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a passes in the common lead frame 10 (Para 0021). Regarding claim 11, Masao (see, e.g., FIG. 2, FIG. 6) discloses a processing of: forming a planar shape of a common lead frame 10 that can be used for both a first package 20, for lower left package region 10a and a second package 20, for middle left package region 10a, based on specifications of each of a first chip 21, on lower left die pad 11 used in the first package 20, for lower left package region 10a and a second chip 21, on middle left die pad 11 used in the second package 20, for middle left package region 10a (Para 0021, Para 0023); and making a thickness of at least a part of a lead portion 12, outer portion (see FIG. 6) through which any one of a first cutting line C1, e.g., upper side of lower left package region 10a corresponding to an outer peripheral side e.g., upper side of lower left package region 10a of the first package 20, for lower left package region 10a and a second cutting line C1, e.g., upper side of middle left package region 10a corresponding to an outer peripheral side e.g., upper side of middle left package region 10a of the second package 20, for middle left package region 10a passes smaller than a thickness of a lead portion 12 through which the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a do not pass in the common lead frame 10 (Para 0035, Para 0045), Although Masao discloses substantial features for claimed invention, Masao fails to expressly teach a control program for causing a computer to execute processing of the method. Kierse (see, e.g., FIG. 2A – FIG. 2L) teaches a control program for causing a computer to execute processing e.g., dry or wet etching system for the purpose of producing a plurality of smooth recessed region in a lead frame (Para 0050-Para 0054). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a common lead frame that can be used for both a first package and a second package and making a portion of a lead portion smaller of Masao to include a control program for causing a computer to execute processing as described by Kierse for the purpose of producing a plurality of smooth recessed region in a lead frame (Para 0054). Regarding claim 12, Masao (see, e.g., FIG. 2, FIG. 6) teaches the control program according to claim 11, further causing the computer to execute processing of forming a through hole e.g., space created by cutting area 46 in at least a part of a lead portion 12 through which any one of the first cutting line C1, e.g., upper side of lower left package region 10a and the second cutting line C1, e.g., upper side of middle left package region 10a passes in the common lead frame 10 (Para 0021). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Aug 21, 2023
Application Filed
Apr 20, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672428
DISPLAY DEVICE
4y 5m to grant Granted Jun 30, 2026
Patent 12668414
PACKAGE FOR SILICON PHOTONICS DEVICE AND IMPLEMENTATION METHOD THEREOF
3y 4m to grant Granted Jun 30, 2026
Patent 12672408
LED DISPLAY UNIT GROUP, MANUFACTURING METHOD OF LED DISPLAY UNIT GROUP, AND DISPLAY PANEL
3y 0m to grant Granted Jun 30, 2026
Patent 12672461
DISPLAY DEVICE
2y 10m to grant Granted Jun 30, 2026
Patent 12666979
SEMICONDUCTOR PACKAGE AND METHOD
2y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
68%
With Interview (-13.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 451 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month