DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 3/16/2026 has been considered.
Response to Arguments
Applicant's arguments with respect to claims 1-8 and 10-20 have been considered but are moot because the arguments do not apply to all of the references being used in the current rejection. Specifically, Applicant s arguments filed 3/16/2026 applied to the Chiang 534 reference used to reject at least claim 20 in the rejection under 35 USC 102(a)(1). In the current rejection, Applicant s amendment filed 3/16/2026 necessitated the incorporation of a secondary reference Lin 609 to supplement the teachings of Chiang 534 by providing the specifically recited claimed the source/drain regions disposed in recessed regions of the active region on both sides of the gate structure and connected to the plurality of channel layers; the upper surfaces of the internal spacer layers and lower surfaces of the internal spacer layers being in contact with the gate dielectric layer and the source/drain regions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 2020/0227534) in view of Lin (US 2022/0384609).
Regarding claim 20, Chiang discloses, in at least figures 1A-1D and related text, a semiconductor device, comprising:
a substrate (10, [50]);
an active region (region of 10 for GAA FET device, [46]-[49], [50], figures) disposed on the substrate (10, [50]) and extending in a first direction (X direction, figures);
a gate structure (82/84, [52]) disposed on the substrate (10, [50]), overlapping the active region (region of 10 for GAA FET device, [46]-[49], [50], figures), extending in a second direction (Y direction, figures), and including a gate dielectric layer (82, [52]) and a gate electrode (84, [52]);
a plurality of channel layers (25, [50], [52]) disposed on the active region (region of 10 for GAA FET device, [46]-[49], [50], figures) and spaced apart from each other in a vertical direction (Z direction, figures) perpendicular to an upper surface of the substrate (10, [50]);
source/drain regions (50, [53]) disposed in recessed regions of the active region (region of 10 for GAA FET device, [46]-[49], [50], figures) on both sides of the gate structure (82/84, [52]) and connected to the plurality of channel layers (25, [50], [52]); and
internal spacer layers (35, [53]) paced apart from the plurality of channel layers (25, [50], [52]),
wherein the gate structure (82/84, [52]) includes an upper portion (uppermost 82/84, [52], figures) disposed on an uppermost channel layer among the plurality of channel layers (25, [50], [52]), and a plurality of lower portions (lower 82/84, [52], figures), each disposed below a channel layer among the plurality of channel layers (25, [50], [52]), in a region vertically overlapping the plurality of channel layers (25, [50], [52]),
wherein the internal spacer layers (35, [53]) are disposed between the lower portions (lower 82/84, [52], figures) and the source/drain regions (50, [53]),
wherein a portion of the gate dielectric layer (82, [52]) is disposed between the internal spacer layers (35, [53]) and the plurality of channel layers (25, [50], [52]), and the internal spacer layers (35, [53]) and the plurality of channel layers (25, [50], [52]) are spaced apart from each other.
Chiang does not explicitly disclose source/drain regions disposed in recessed regions of the active region on both sides of the gate structure and connected to the plurality of channel layers; upper surfaces of the internal spacer layers and lower surfaces of the internal spacer layers are in contact with the gate dielectric layer and the source/drain regions.
Lin teaches, in at least figure 19, and related text, the device comprising source/drain regions (1202, [33]) disposed in recessed regions of the active region on both sides of the gate structure (1602, [39]) and connected to the plurality of channel layers (306, [18]); upper surfaces of the internal spacer layers (1102, [31]) and lower surfaces of the internal spacer layers (1102, [31]) are in contact with the gate dielectric layer (1502/1604, [38], [39]) and the source/drain regions (1202, [33]), for the purpose of improving the short channel effect (SCE), the carrier mobility, and the sub-threshold leakage current of the SRAM and logic cells having such GAA devices ([51]).
Chiang and Lin are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chiang with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chiang to have the source/drain regions disposed in recessed regions of the active region on both sides of the gate structure and connected to the plurality of channel layers; the upper surfaces of the internal spacer layers and lower surfaces of the internal spacer layers being in contact with the gate dielectric layer and the source/drain regions, as taught by Lin, for the purpose of improving the short channel effect (SCE), the carrier mobility, and the sub-threshold leakage current of the SRAM and logic cells having such GAA devices ([51], Lin).
Allowable Subject Matter
Claims 1-8 and 10-12 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 that recite "the first gate dielectric layer and the second dielectric layer overlap the source/drain regions in the vertical direction" in combination with other elements of the base claims 1.
Claims 13-19 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 13 that recite "first surfaces among surfaces in contact with the source/drain regions and the gate dielectric layer have a (111) crystal orientation" in combination with other elements of the base claims 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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