DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 and Modification A2 (claims 1-20) in the reply filed on 06 March 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation, “the second surfaces of the isolation regions and the substrate”, in lines 4-5 of the claim. There is insufficient antecedent basis for the phrase “the second surfaces of the isolation regions”. It is unclear if this phrase refers to the generic second surface recited in claim 9 by the limitation, “between a second surface and the substrate”, or if this phrase refers to a newly defined second surfaces of a specific region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US PGPub 20190287994 A1; hereinafter referred to as “Tanaka”) in view of Kanamori et al. (US PGPub 20210091093 A1; hereinafter referred to as “Kanamori”) and further in view of Ryu et al. (US PGPub 20210143160 A1; hereinafter referred to as “Ryu”).
Re claim 1: Tanaka teaches a semiconductor device comprising: a substrate (para. 52); first gate electrodes spaced apart from each other and stacked on the substrate (FIG. 4, 18: el. 22; para. 82, 123-124); first channel structures extending through the first gate electrodes in a first direction that is perpendicular with respect to a surface of the substrate (FIG. 18: el. 24, 27; para. 83|first channel structures extend through first gate electrodes 22, include channel layers 27, and further include and are enclosed by first dielectric layers 24), wherein each of the first channel structures respectively includes a first channel layer (FIG. 18: el. 27; para. 85) and a first dielectric layer (FIG. 18: el. 24; para. 83) between the first channel layer and each of the first gate electrodes (FIG. 18; para. 83); separation regions (FIG. 3: el. SLT; para. 74) extending through the first gate electrodes in the first direction and extending in a second direction that is parallel with respect to the surface of the substrate (FIG. 3: el. SLT; para. 74|z-direction of FIG. 3 corresponds to the first direction, y-direction of FIG. 3 corresponds to second direction), and wherein adjacent ones of the separation regions are spaced apart from each other in a third direction that is perpendicular with respect to the first and second directions and that is parallel with respect to the surface of the substrate (FIG. 3: el. SLT; para. 74|regions SLT spaced apart in FIG. 3 in the x-direction, which corresponds to the third direction); an insulating layer on the first channel structures (FIG. 18: el. 45; para. 82, 86); a plurality of conductive patterns passing through the insulating layer (FIG. 18: el. 30; para. 86), wherein each of the conductive patterns is connected to a respective one of the first channel structures (FIG. 18: el. 30, 24-27; para. 86); a second gate electrode on the insulating layer (FIG. 18: el. SGD; para. 82, 222|second gate electrode shown as a layered structure in FIG. 18, para. 222 teaches the second gate electrode as being optionally formed as a single layer structure); second channel structures extending through the second gate electrode (FIG. 18: el. SHa; para. 87), wherein each of the second channel structures respectively includes a second channel layer (FIG. 18: el. 35; para. 87) connected to a respective one of the conductive patterns (FIG. 18: el. 30; para. 87) and a second dielectric layer (FIG. 18: el. 31; para. 87) between the second channel layer and the second gate electrode (FIG. 18: para. 87); and isolation regions (FIG. 18: el. 36; para. 93) extending through the second gate electrode, wherein the insulating layer is between the isolation regions and the substrate (FIG. 18: el. 36; para. 93, 86|Tanaka teaches a separation insulation film 36 provided above the memory pillar MH; the top surface of the memory pillar is formed by the top surface of the layer including the conductive patterns 30 in the insulating layer 45), wherein each of the first channel structures includes a respective first region overlapping a respective one of the second channel structures in the first direction (FIG. 3: el. SH), and a respective second region that is non-overlapping with the respective one of the second channel structures in the first direction (FIG. 18: el. SHa, 24-27; FIG. 3: el. SH, MH|FIG. 3 shows a portion of the first channel pillar MH overlapping the second channel structures SH and a portion of the first channel pillar MH which does not overlap the second channel structure SH). Tanaka teaches a separation region in a top-down view of the device, but is silent regarding integrating this feature in a cross-section and is silent as to the height of this feature in a cross-section. Tanaka also teaches a difficulty in forming separation regions and second channel structures in close proximity (para. 78, 118). Tanaka fails to teach wherein each of the second channel structures includes a first portion having a first width in the third direction and a second portion having a second width in the third direction that is greater than the first width, wherein the first portion is between the second portion and the substrate.
In a similar field of endeavor, Kanamori teaches a semiconductor memory device comprising second channel structures and isolation regions extending through a second gate electrode above first channel structures and separation regions extending through first gate electrodes (FIG. 2E: VC2, SSP, 50, VC1, 83, 81). Kanamori teaches a semiconductor device comprising separation regions (FIG. 2E: el. 83; FIG. 1: el. WS; para. 57, 22) extending through the first gate electrodes in the first direction and extending in a second direction that is parallel with respect to the surface of the substrate (FIG. 2E: el. 83; FIG. 1: el. WS), and wherein adjacent ones of the separation regions are spaced apart from each other in a third direction that is perpendicular with respect to the first and second directions and that is parallel with respect to the surface of the substrate (FIG. 2E: el. 83; FIG. 1: el. WS); an insulating layer (FIG. 2E: el. 49; para. 57) on the first channel structures and the separation regions (FIG. 2E: el. 49, VC1, 83), wherein the separation regions are between the insulating layer and the substrate (FIG. 2E: el. 83, 49, 10). Kanamori further teaches isolation regions (FIG. 2E: el. SSP; para. 22) extending through the second gate electrode (FIG. 2E: el. 50; para. 57), wherein the insulating layer is between the isolation regions and the substrate (FIG. 2E: el. 49, SSP, 10). Kanamori also teaches
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings Tanaka and Kanamori, to enable using the separation regions of Kanamori in the semiconductor device of Tanaka, for the benefit of simplifying a manufacturing process by using a known method for integrating separation regions into a semiconductor memory device having two channel levels being vertically displaced and for the benefit of decreasing a difficulty in forming second channel structures by decreasing a proximity of second channel structures and separation regions.
In a similar field of endeavor, Ryu teaches a semiconductor memory device comprising second channel structures extending through a second gate electrode above first channel structures extending through first gate electrodes (FIG. 10K: el. 160, 150’, CH, 110). Ryu teaches a semiconductor device comprising second channel structures (FIG. 10J-10K: el. 170b, 160; para. 131-134) extending through the second gate electrode (FIG. 10K: el. 150’; para. 115), wherein each of the second channel structures respectively includes a second channel layer (FIG. 10K: el. 160) and a second dielectric layer (FIG. 10J: el. 170b; para. 131-132) between the second channel layer and the second gate electrode (FIG. 10J: el. 170b, 160, 150’) wherein each of the second channel structures includes a first portion having a first width (annotated FIG. 10K: el. w1| first width shown in annotated FIG. 10K provided below) in the third direction and a second portion having a second width in the third direction that is greater than the first width (annotated FIG. 10K: el. w2, w1| second width of second portion greater than first width of first portion as shown in annotated FIG. 10K provided below), wherein the first portion is between the second portion and the substrate (annotated FIG. 10K provided below). Ryu also teaches a benefit of forming a second portion of a second channel structure with a greater width than lower portions of a second channel structure is that it reduces a difficulty in forming upper interconnections while still allowing for the improved integration density provided by narrow overall channel widths (para. 68).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings Tanaka and Ryu, to enable using the width of the second portions of the second channel structures of Ryu in the second portions of the second channel structures of the semiconductor device of Tanaka, for the benefit of decreasing a difficulty in forming upper interconnections to second channel structures.
Re claim 2: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein each of the conductive patterns includes a first side surface in contact with the insulating layer such that the respective one of the first channel structures is between the first side surface and the substrate in the first direction, and a second side surface in contact with the insulating layer such that the second side surface is spaced apart from the respective one of the first channel structures in the third direction (Tanaka - FIG. 18: el. 30|a side surface of the conductive pattern 30 is above the first channel structure, and a second side surface of the conductive pattern 30 is spaced apart from the first channel structure in the x-direction, corresponding to the third direction; first and second side surfaces labelled in annotated FIG. 18 provided below).
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Re claim 3: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein a thickness of the second gate electrode is greater than a thickness of each of the first gate electrodes (Kanamori - FIG. 2E: el. 50, 81), and wherein each of the first gate electrodes includes a first material, and wherein the second gate electrode includes a second material different than the first material (Kanamori - para. 33-35|second gate electrode formed with an upper silicide layer to decrease resistance of second gate electrode (string select gate electrode); first gate electrodes formed of metal such as tungsten).
Re claim 4: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein the first portion extends through the second gate electrode, and wherein the second gate electrode is between the second portion and the substrate (Ryu - FIG. 10K: el. 160, 150’, 101|annotated FIG. 10K labelling first and second portion of second channel structure provided in Re claim 1 section).
Re claim 5: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein each of the second channel structures further includes a third portion extending from the first portion toward the substrate, and wherein the third portion has a third width greater than the first width (Ryu – annotated FIG. 10K provided below).
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Re claim 6: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 5, wherein the third portion is between the second gate electrode and the substrate (Ryu - FIG. 10K: el. 160, 101, 150'| annotated FIG. 10K with labelled third portion provided in Re claim 5 section).
Re claim 7: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 5, wherein each of the second channel structures further comprises a semiconductor spacer layer (Tanaka - FIG. 18: el. 34; para. 87) between the second channel layer (Tanaka - FIG. 18: el. 35; para. 87) and the second dielectric layer in the first portion and in the second portion (Tanaka - FIG. 18: el. 34, 35, 31|annotated FIG. 18 provided below), and wherein the second channel layer is in direct contact with the second dielectric layer in the third portion (Tanaka - FIG. 18: el. 35, 31|annotated FIG. 18 provided below).
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Re claim 8: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein the second width of the second portion is greater than a width of each of the first channel structures in the third direction (Ryu - FIG. 10K: el. CH |annotated FIG. 10K provided below).
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Re claim 9: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein each of the isolation regions (Ryu – FIG. 10K: el. 150R) includes a first surface between a second surface and the substrate, and wherein a distance between the second surfaces and the substrate is less than a distance between the substrate and surfaces of the second portions of the second channel structures that are spaced apart from the second gate electrode (Ryu - FIG. 10K: el. 150R, 101, 160|annotated FIG. 10K provided below).
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Re claim 10: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 9, wherein each of the second channel structures includes a bent portion defined by the first portion and the second portion, wherein the bent portion is adjacent to the second gate electrode, and wherein a distance between the bent portion and the substrate is the same as the distance between the second surfaces of the isolation regions and the substrate (Ryu - FIG. 10K|annotated FIG. 10K, provided in Re claim 9 section, shows the distance between bent portions and the substrate and the distance between an upper surface of isolation region and the substrate are equivalent).
Re claim 11: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, wherein the first dielectric layer has a multi-layer structure, and wherein the second dielectric layer has a single layer structure (Ryu - FIG. 10K).
Re claim 12: The combination of Tanaka, Kanamori, and Ryu teaches the semiconductor device of claim 1, further comprising a cell region insulating layer (Tanaka - FIG. 18: el. 44; para. 82) on the first gate electrodes (Tanaka - FIG. 18: el. 22) and on side surfaces of the first channel structures (Tanaka - FIG. 18: el. 24|side surface of the first channel structure formed by dielectric layer 24), wherein the cell region insulating layer is between the insulating layer and the first gate electrodes (Tanaka - FIG. 18: el. 44, 45, 22), wherein each of the first channel structures includes a first channel pad (Tanaka - FIG. 18: el. 29; para. 84) connected to the first channel layer (Tanaka - FIG. 18: el. 27), wherein each of the conductive patterns includes a first conductive portion on the cell region insulating layer and a second conductive portion on the first channel pad (Tanaka - FIG. 18|annotated FIG. 18 provided below), and wherein a distance between the first conductive portion and the substrate is greater than a distance between the second conductive portion and the substrate (Tanaka - FIG. 18|additional annotated FIG. 18 provided in second figure below).
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Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Ryu.
Re claim 13: Tanaka teaches a semiconductor device comprising: a substrate (para. 52); gate electrodes spaced apart from each other and stacked in a first direction that is perpendicular with respect to a surface of the substrate (FIG. 4, 18: el. 22; para. 82, 123-124); channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer and a dielectric layer between the channel layer and the gate electrodes (FIG. 18: el. 24, 27; para. 83|channel structures extend through gate electrodes 22, include channel layers 27, and further include and are enclosed by first dielectric layers 24); an insulating layer on the channel structures (FIG. 18: el. 45; para. 82, 86); a conductive pattern passing through the insulating layer and connected to the channel structures (FIG. 18: el. 30; para. 86); an upper horizontal conductive layer on the insulating layer and the conductive pattern (FIG. 18: el. SGD; para. 82, 222|upper horizontal conductive layer shown as a layered structure in FIG. 18, para. 222 teaches the upper horizontal conductive layer as being optionally formed as a single layer structure), and vertical semiconductor structures connected to the conductive pattern by penetrating through the upper horizontal conductive layer (FIG. 18: el. SHa, 31-35; para. 87), wherein each of the vertical semiconductor structures includes a first portion penetrating through the upper horizontal conductive layer, a second portion on the first portion, and a third portion below the first portion (FIG. 18: el. SHa, 31-35|annotated FIG. 18 provided below). Tanaka fails to teach wherein the second portion covers a portion of an upper surface of the upper horizontal conductive layer, and wherein the third portion covers a portion of a lower surface of the upper horizontal conductive layer.
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In a similar field of endeavor, Ryu teaches a semiconductor memory device comprising vertical semiconductor structures penetrating through an upper horizontal conductive layer above channel structures passing through gate electrodes (FIG. 10K: el. 160, 150’, CH, 110). Ryu teaches a semiconductor device comprising vertical semiconductor structures (FIG. 10J-10K: el. 170b, 160; para. 131-134) penetrating through an upper horizontal conductive layer (FIG. 10K: el. 150’; para. 115) wherein each of the vertical semiconductor structures includes a first portion penetrating through the upper horizontal conductive layer, a second portion on the first portion, and a third portion below the first portion, wherein the second portion covers a portion of an upper surface of the upper horizontal conductive layer, and wherein the third portion covers a portion of a lower surface of the upper horizontal conductive layer (annotated FIG. 10K provided below shows first and third portions covering portions of respective surfaces of upper horizontal conductive layer 150’). Ryu also teaches a benefit of forming a second portion of a second channel structure with a greater width than a first portion which penetrates through the upper horizontal conductive layer is reduced difficulty in forming upper interconnections while still allowing for the improved integration density provided by narrow overall channel widths (para. 68), and further teaches that the step of forming the second channel structure hole expands the width of both the second and third portions (FIG. 10E-10F; para. 121-122).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings Tanaka and Ryu, to enable using the width of the second and third portions of the second channel structures of Ryu in the second and third portions of the second channel structures of the semiconductor device of Tanaka, for the benefit of decreasing the difficulty in forming upper interconnections to second channel structures.
Re claim 14: The combination of Tanaka and Ryu teaches the semiconductor device of claim 13, wherein the first to third portions are integrally connected, and wherein a first width of the first portion is smaller than a second width of the second portion or a third width of the third portion (Ryu - FIG. 10K|integral connection of first, second, and third portions and smaller width of first portion is shown in annotated FIG. 10K provided in Re claim 13 section).
Re claim 15: The combination of Tanaka and Ryu teaches the semiconductor device of claim 13, wherein the upper horizontal conductive layer is a string select gate electrode, and wherein the vertical semiconductor structure is a string select channel structure (Ryu – para. abstract, 115, 134|upper horizontal layer 150’ is a string select gate electrode, vertical semiconductor structure including channel layers 160 is a string select channel structure).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Ryu as applied to claim 13 above, and further in view of Kanamori.
Re claim 16: The combination of Tanaka and Ryu teaches the semiconductor device of claim 13, further comprising separation regions (Tanaka - FIG. 3: el. SLT; para. 74) passing through the gate electrodes, extending in the first direction and in a second direction that is parallel with respect to the surface of the substrate (Tanaka - FIG. 3: el. SLT; para. 74|z-direction of FIG. 3 corresponds to the first direction, y-direction of FIG. 3 corresponds to second direction), and spaced apart from each other in a third direction that is parallel with respect to the surface of the substrate (Tanaka - FIG. 3: el. SLT; para. 74|regions SLT spaced apart in FIG. 3 in the x-direction, which corresponds to the third direction). The combination of Tanaka and Ryu fails to teach wherein the upper horizontal conductive layer is located at a higher level than a level of the separation regions. Tanaka also teaches a difficulty in forming separation regions and vertical semiconductor structures in close proximity (para. 78, 118).
In a similar field of endeavor, Kanamori teaches a semiconductor memory device comprising vertical semiconductor structures and isolation regions extending through an upper horizontal conductive layer above channel structures and separation regions passing through gate electrodes (FIG. 2E: VC2, SSP, 50, VC1, 83, 81). Kanamori teaches a semiconductor device comprising separation regions (FIG. 2E: el. 83; FIG. 1: el. WS; para. 57, 22) passing through gate electrodes, extending in the first direction and in a second direction that is parallel with respect to the surface of the substrate (FIG. 2E: el. 83; FIG. 1: el. WS), and spaced apart from each other in a third direction that is parallel with respect to the surface of the substrate (FIG. 2E: el. 83; FIG. 1: el. WS), wherein the upper horizontal conductive layer is located at a higher level than a level of the separation regions (FIG. 2E: el. 50, 83).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Tanaka and Ryu and the teachings of Kanamori, to enable using the separation regions of Kanamori in the semiconductor device of the combination of Tanaka and Ryu, for the benefit of simplifying a manufacturing process by using a known method for integrating separation regions into a semiconductor memory device which provides the benefit of decreasing a difficulty in forming vertical semiconductor structures by decreasing a proximity of separation regions and vertical semiconductor structures.
Re claim 17: The combination of Tanaka, Ryu, and Kanamori teaches the semiconductor device of claim 16, further comprising isolation regions (Kanamori - FIG. 2E: el. SSP; para. 22) located at a level higher than the level of the separation regions (Kanamori - FIG. 2E: el. SSP, 83), penetrating through the upper horizontal conductive layer (Kanamori - FIG. 2E: el. SSP, 50), and spaced apart from each other in the third direction, wherein in a plane, a distance between the separation regions adjacent to each other is greater than a distance between the isolation regions adjacent to each other (Kanamori - FIG. 2E: el. SSP, 83).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 20220262819 A1; hereinafter referred to as “Kim”) in view of Ryu.
Re claim 18: Kim teaches a data storage system (para. 120-123; FIG. 14) comprising: a semiconductor storage device (FIG. 14: el. 1100; FIG. 10: el. 400; para. 123) including, a first substrate (FIG. 10: el. 301; para. 84), circuit elements on one side of the first substrate (FIG. 10: el. 360; para. 84), a second substrate on the circuit elements (FIG. 10: el. 401; para. 87), gate electrodes spaced apart from each other and stacked in a first direction that is perpendicular with respect to a surface of the second substrate (FIG. 10: el. 430; para. 87), wherein the gate electrodes are stacked between the first and second substrates (FIG. 10: el. 430, 301, 401), channel structures extending through the gate electrodes in the first direction, wherein each of the channel structures respectively includes a channel layer and a dielectric layer between the channel layer and the gate electrodes (FIG. 10: el. 460; FIG. 4: el. 160, 164, 162; para. 88, 47), an insulating layer on the channel structures, a plurality of conductive patterns passing through the insulating layer, wherein each of the conductive patterns is connected to a respective one of the channel structures (FIG. 10|upper interconnect layers including conductive contact layer 470 are connected to channel structures and embedded in an insulating layer on the channel structures), and an input/output pad electrically connected to at least one of the circuit elements (FIG. 14: el. 1101; para. 129); and a controller (FIG. 14: el. 1200; para. 129) electrically connected to the semiconductor storage device through the input/output pad (FIG. 14: el. 1101, 1200), wherein the controller is configured to control the semiconductor storage device (para. 130-131). Kim fails to teach a conductive layer on the insulating layer and the conductive patterns, a plurality of semiconductor structures extending through the conductive layer, wherein each of the semiconductor structures is connected to a respective one of the conductive patterns, and wherein each of the semiconductor structures includes a first portion extending through the conductive layer, a second portion on the first portion, and a third portion between the first portion and the gate electrodes, wherein the second portion is on a portion of a first surface of the conductive layer opposite the gate electrodes, and wherein the third portion is on a portion of a second surface of the conductive layer adjacent the gate electrodes.
In a similar field of endeavor, Ryu teaches a semiconductor storage device (FIG. 1: el. 10; para. 26) including circuit elements (FIG. 1: el. 30; para. 26) and a memory region (FIG. 1: el. 20; para. 26) including channel structures extending through gate electrodes (FIG. 4A). Ryu teaches channel structures extending through the gate electrodes in the first direction (FIG. 4A: el. CH, 130; para. 39), wherein each of the channel structures respectively includes a channel layer (FIG. 4A: el. 140; para. 39) and a dielectric layer (FIG. 4A: el. 145; para. 47) between the channel layer and the gate electrodes, an insulating layer on the channel structures (FIG. 4A: el. 170L; para. 56), a plurality of conductive patterns passing through the insulating layer (FIG. 4A, 4B|annotated FIG. 4B labelling the conductive patterns provided below), wherein each of the conductive patterns is connected to a respective one of the channel structures (FIG. 4A, 4B |annotated FIG. 4B provided below), a conductive layer on the insulating layer and the conductive patterns (FIG. 4A: el. 150; para. 39|conductive layer 150 on insulating layer 170L and conductive patterns with the insulating layer), a plurality of semiconductor structures extending through the conductive layer (FIG. 4A: el. 160; para. 39), wherein each of the semiconductor structures is connected to a respective one of the conductive patterns, and wherein each of the semiconductor structures includes a first portion extending through the conductive layer, a second portion on the first portion, and a third portion between the first portion and the gate electrodes, wherein the second portion is on a portion of a first surface of the conductive layer opposite the gate electrodes, and wherein the third portion is on a portion of a second surface of the conductive layer adjacent the gate electrodes (FIG 4A, 4B|annotated FIG. 4B provided below illustrates and labels first, second, and third portions of the semiconductor structure which passes through conductive layer 150 and is above a height of the gate electrodes 130). Ryu also teaches a benefit of forming a second portion of a semiconductor structure on a first surface of the conductive layer is that it reduces a difficulty in forming upper interconnections and a benefit of multiple vertical channel structures with narrow overall channel widths is improved integration density (para. 3, 4, 68).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings Kim and Ryu, to enable using the semiconductor structures with second and third portions on a conductive layer of Ryu in the semiconductor storage device of Kim, for the benefit of increased integration density while enabling reduced difficulty in forming reliable upper interconnections.
Re claim 19: The combination of Kim and Ryu teaches the data storage system of claim 18, wherein each of the channel structures includes a first region at least partially overlapping a respective one of the semiconductor structures in the first direction, and a remaining second region, and wherein the first portion has a first width in a second direction that is perpendicular with respect to the first direction, wherein the second portion has a second width in the second direction, wherein the first width of the first portion is less than the second width of the second portion (Ryu - FIG. 4A, 4B|annotated FIG. 4B provided below illustrates and labels the first region and second region and the smaller width of the first portion as compared to the width of the second region).
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Re claim 20: The combination of Kim and Ryu teaches the data storage system of claim 19, further comprising: a plurality of isolation regions (Ryu – FIG. 4A: el. 150R; para. 53) extending through the conductive layer, wherein each of the isolation regions extends in a third direction that is perpendicular with respect to the first and second directions (Ryu – FIG. 4A: el. 150R; para. 53|isolation regions extend in the y-direction, which is perpendicular to the second and first directions as used in claims 18, 19, and as shown in annotated FIG. 4B in Re claim 19 section), and wherein each of the isolation regions is spaced apart from the gate electrodes (Ryu – FIG. 4A: el. 150R, 130).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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