DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election without traverse on January 21, 2026, non-elected claims 16-19 are withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes FORMING A HIGH ENERGY RADIATION DETECTOR WITH EXPOSED INSULATING LAYER
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “forming at least one first guard ring contact region, which is p+-doped in the semiconductor body at the first main side, wherein the at least one first guard ring contact region running around and a distant from an entrance window, seen in top view of the entrance window, and wherein the at least one first guard ring contact region is electrically contacted by a first guard contact running through the bottom insulation layer and the reinforcing layer.” The bolded portion does not make sense.
Claim 12 has not been rejected over the prior art because, in light of the 35 U.S.C. 112 rejections supra, there is sufficient uncertainty that it would not be proper to reject the claims on the basis of prior art. As stated in In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 8, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Szeles, US 2008/0203514 A1.
Claim 1: Szeles discloses
providing a semiconductor body (1) with a first main side (top, FIG. 8) and an opposite, second main side (bottom), wherein the semiconductor body is configured to detect radiation with an energy of at least 10eV (“x-ray”, [0011]), and wherein the first main side includes a radiation entrance area for the radiation;
generating a bottom insulation layer (22) located directly at the first main side, the bottom insulation layer comprising a first electrically insulating material ([0040]);
applying a sacrificial layer (24) directly on the bottom insulation layer across the entrance area so that throughout the entrance area the bottom insulation layer is between the semiconductor body and the sacrificial layer (FIG. 4);
applying a reinforcing layer (26) over the bottom insulation layer so that the sacrificial layer is sandwiched between the bottom insulation layer and the reinforcing layer, the reinforcing layer comprising a second electrically insulating material;
and exposing the bottom insulation layer from the sacrificial layer and from the reinforcing layer in the entrance area, wherein the bottom insulation layer and the reinforcing layer remain directly on top of each other in at least one insulation region of the first main side outside the entrance area (FIG. 8).
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Claim 3: the bottom insulation layer is generated with a constant thickness all over the first main side, and wherein a final thickness of the bottom insulation layer in the entrance area, after exposing the bottom insulation layer from the sacrificial layer and from the reinforcing layer, is the same as a thickness of the bottom insulation layer immediately after generating the bottom insulation layer (FIG. 8).
Claim 8: Szeles discloses applying a protection layer on top of the reinforcing layer, wherein exposing the bottom insulation layer from the sacrificial layer and from the reinforcing layer includes exposing the bottom insulation layer from the protection layer, and wherein a plurality of holes are formed through the protection layer outside the entrance area for electrically contacting the semiconductor body. As no distinction is made between the protection layer and the reinforcing layer, the protection layer can be the outer part of 26, and the reinforcing layer the inner part of 26. Note that the outer part of 26 will be applied after the inner part is already there.
Claim 15: the bottom insulator layer and the reinforcing layer are applied all over the first main side continuously and as closed layers (FIG. 3).
Claim 20: Szeles discloses
providing a semiconductor body (2) with a first main side (top, FIG. 8) and an opposite, second main side (bottom), wherein the semiconductor body is configured to detect radiation with an energy of at least 10eV (“x-ray”, [0011]), and wherein the first main side includes a radiation entrance area for the radiation;
generating a bottom insulation layer (22) located directly at the first main side, the bottom insulation layer comprising a first electrically insulating material;
applying a sacrificial layer (24) directly on the bottom insulation layer across the entrance area so that throughout the entrance area the bottom insulation layer is between the semiconductor body and the sacrificial layer (FIG. 8, FIG. 4);
and exposing the bottom insulation layer from the sacrificial layer in the entrance area, and wherein the bottom insulation layer remains in at least one insulation region of the first main side outside the entrance area (FIG. 8, FIG. 5). Note that FIG. 8 is an alternation of the method of FIGS. 2-7 where layer 22 is not removed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Szeles in view of Orava, US 6,215,123 B1.
Claim 7: Szeles discloses that exposing the bottom insulation layer from the sacrificial layer and from the reinforcing layer in the entrance area comprises:
removing the reinforcing layer by a first etching method “If protective film 26 is a photoresist, apertures 34 are formed therein by selectively etching soluble portions of the photoresist.” [0044].
Szeles does not disclose specifically the etching of the sacrificial layer; however, etching the photoresist and etching the target layer are typically done separately. See e.g. Orava FIGS. 3C-3E, first etching the photoresist 12, and then in a second step etching the target layer 11. It would have been obvious to do this in separate steps as the ordinary technique in the art.
The etching of the sacrificial layer is selective relative to the bottom insulation layer, as the bottom insulating layer is not removed in the embodiment of FIG. 8.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Szeles.
Claim 11 recites that a thickness of the bottom insulation layer, as generated, is at least 0.03µm and at most 0.16µm ([0052]), “desirably 100 Angstroms and more desirably 25 Angstroms”. The ranges are largely overlapping, and it would have been obvious for those in the art to select a thickness in the claimed range given the guidance of Szeles.
Claim 11 recites that a thickness of the reinforcing layer, as applied, is at least 0.05µm and at most 0.3µm and is larger than the thickness of the bottom insulation layer, as generated, and wherein a thickness of the sacrificial layer, as applied, is at least 0.1µm and at most 0.6µm. Changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV).
Claim 13: the bottom insulation layer and the reinforcing layer are also generated on the second main side with the same thicknesses as on the first main side (FIG. 2), respectively. Szeles discloses a single thickness for layer 22, and through methods that would be expected to generate uniform thickness. Thus the subject matter of claim 13 is suggested by Szeles.
Allowable Subject Matter
Claims 2, 4-6, 9, 10, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 2, Szeles discloses “a thin oxide film 22 of native oxides of CdZnTe, such as Cd(Zn)TeOx, TeOx, CdO or ZnO, is formed on substrate 2 by UV/Ozone oxidation.” [0040]. It is not clear that it would be obvious to substitute thermal oxidation.
With respect to claims 4, there are not p+ cathode regions disclosed.
With respect to claims 9 and 10, Szeles does not disclose a protection layer or reinforcing layer of a nitride produced by plasma enhanced chemical vapor deposition.
With respect to claim 14, Szeles does not disclose the claimed drift ring contact regions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited: Zorzi, US 2019/0011577 A1, discloses p+ regions 12 under an insulating layer 15, but does not disclose the reinforcement layer, or disclose that the p+ regions are formed after the bottom insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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