DETAILED ACTION
Claims 21-23 and 25-41 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner recommends inserting --from an Active Context-- at the end.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 24, line 6, insert --a-- after “by”.
In paragraph 24, 2nd to last line, delete “from” after “read”.
In paragraph 55, 2nd to last line, replace “105” with --205--.
In paragraph 70, line 5, replace “a instruction” with --an instruction--.
Appropriate correction is required.
Claim Objections/Inquiries
In claim 23 (and similarly claim 33), does applicant mean for the particular set to write to elements of the first context? In the last paragraph of claim 21, the first processor/context appears to be active and it is the second context that is inactive. Is the particular set not for the second context? The examiner notes that the claim is not incorrect; claim 23 would simply cover both the first and second contexts becoming inactive. However, the examiner is unsure this is what was intended.
Claim 37 is objected to because of the following informalities:
In line 6, delete “and”.
Appropriate correction is required.
Claim Interpretation
The examiner notes that the interpretations that appear in the “Claim Interpretation” section of the previous office action are no longer applicable due to amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-23 and 25-41 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claims 21, 31, and 37, applicant now claims detecting a particular set of coprocessor instructions (plural) that indicates that an active context is to become inactive. Paragraph 34 states “rename logic 205 may be coupled to an instruction decoder (not shown in Fig. 2) and may detect the presence of such instructions that, responsive to their decoding, indicate that a context becoming inactive is imminent.” However, this appears to be the only portion of the specification that discusses detecting plural instructions that indicate a context is to become inactive. Paragraph 56, detects the presence of a single clear instruction that indicates a context is to become inactive. Elsewhere, in paragraphs 24, 55, 70, execution of a single clear instruction causes a context to become inactive. Thus, even though paragraph 34 may provide literal support for the claim language, applicant has not adequately described what set of instructions is detected to indicate a context is to be inactive. The clear instruction alone, by setting a register to zeros, seems to be all that is needed to indicate the upcoming inactivity. No other specific instruction, either in addition to the clear instruction to create a set, or as part of a set of instructions in place of the clear instruction, has been described in a way that would allow one of ordinary skill in the art to conclude that applicant possessed the claimed set at the time of filing.
Referring to claims 23 and 33, the examiner has been unable to find support for a set of instructions that indicates an active context is to become inactive and that sets multiple storage elements corresponding to the first context. As explained above, the examiner can only find support for a single clear instruction to set a single register. Where is the support for multiple instructions setting multiple registers of the first context?
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-23 and 25-41 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 21, 31, and 37, the scope of “detect a particular set of coprocessor instructions that indicates that an active context is to become inactive” is unclear. As described above, specification only seems to provide the example of detecting a single clear instruction that indicates that a context is to become inactive. A single clear instruction is not a set of plural instructions. It is not clear if applicant is actually looking for a set of plural instructions, or if applicant is trying to claim that multiple clear instructions are detected, and each indicates that an active context is to become inactive, or if a mistake was made and applicant meant to detect a single instruction to detect the upcoming inactivity. Thus, because the claims are inconsistent with the specification (see MPEP 2173.03), and the examiner does not know how to interpret the claims, the claims are indefinite. The claims will be interpreted as written, where multiple instructions will be detected to indicate a single active context is to become inactive.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 21, last line (and similarly in each of claims 31 and 35), “the first processor”. Does applicant mean --the first one of the plurality of processors--?
In claim 37, “the particular processor”. Does applicant mean --the particular one of the plurality of processors--?
All dependent claims are rejected due to their dependence on an indefinite claim.
Allowable Subject Matter
Claim 21-23 and 25-41 are allowed over the prior art. Note that any amendments to address 112 rejections may affect allowability.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 21, 31, and 37, the prior art of record, either individually or in combination, and together with all other claimed features, has not taught to detect a particular set of coprocessor instructions that indicates that an active context is to become inactive, which is interpreted as detecting a group of multiple instructions that indicates a single active context is to become inactive.
Response to Arguments
On pages 13-14 of applicant’s response, applicant asks that the double-patenting rejection be held in abeyance.
This request is moot due to the withdrawal of the double-patenting rejection based on applicant’s amendments. However, should applicant amend to address 112 rejections, the double-patenting rejection may be reinstated.
On pages 14-15 of applicant’s response, applicant argues that the prior art has not taught the claimed detecting of the set of instructions that indicates that an active context is to become inactive.
The examiner agrees and notes that the prior art rejections have been overcome. However, changes to the claims to address 112 rejections could necessitate a prior art rejection.
On pages 15-16 of applicant’s response, applicant argues that the registers of Chen are part of a unified register file and are not physically distributed among processing elements.
The examiner respectfully disagrees. Different registers are assigned for use by different processing elements of the graphics processor. Thus, they are physically distributed in the sense that a register to hold a result of one processing element is physically assigned/distributed such that its physical storage may be used by that processing element to hold a result.
On pages 16-17, applicant inadequately traverses the examiner’s taking of Official Notice because applicant did not explain why the noticed teaching is not well known in the art. Nevertheless, the examiner directs applicant to the following examples of support for such a teaching:
Beacom (US 5,093,908), in the “Background of the Invention” section, states “Usually the coprocessor is ‘tightly coupled’ to the main processor. The main processor actually fetches all instructions and operands for both the main processor and the coprocessor. The coprocessor merely performs the operations required by the enhanced instructions, such as the addition, subtraction, multiplication, or division of floating-point operands fetched by the main processor.”
Agarwal (US 2002/0156994) states, in paragraph 12, “The host processor is responsible for all instruction fetch intended for host processor and numeric coprocessor. Whenever the host processor fetches an instruction for numeric coprocessor, it automatically passes the instruction to numeric coprocessor.”
MacGregor (US 4,715,013), in the abstract, states “The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word.”
Park (US 2002/0133689), in paragraph 4, states “In a data processing device having a CPU or a main processor, a microprocessor distinct from the main processor, called a coprocessor, is used to perform specified functions that the CPU cannot perform or cannot perform as well and/or as quickly. For example, a coprocessor like a FPU (floating point unit) is a special purpose coprocessor used mainly to perform floating-point operations, vector operations and scalar operations. While a CPU can perform these functions, the coprocessor can perform these functions faster. In such a case, the CPU is used instead to fetch instructions, input or output data, and control program sequences. The CPU actually fetches all instructions and operands for both the main processor and coprocessor. The coprocessor performs the operations specified in the instruction fetched and decoded by the CPU. If the instruction is a data input/output operation, the CPU controls the coprocessor to input or output the data. It is not uncommon that the CPU even controls coprocessor pipelining. That is, the CPU fetches CPU and coprocessor instructions while the coprocessor performs coprocessor operations.”
As such, the examiner asserts that the Official Notice would be supported if prior art
rejections are reinstated.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following prior art made of record by applicant and not relied upon is considered pertinent to applicant's disclosure:
Rappoport (US 2016/0019063) has taught detecting a thread pause instruction, which indicates a context is to become inactive for a predetermined amount of time and allows another thread to use resources associated with the inactive thread (abstract and paragraphs 50-51). A single pause instruction is not the same as the claimed detected set of coprocessor instructions. However, if applicant amends the claim to set forth detecting an instruction, this teaching may be considered for use in a prior art rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights