DETAILED ACTION
Claims 21-40 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (17/644,016) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/644,016 has been considered during examination of the instant application.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because it is inconsistent with the parent disclosure, which was amended to address various objections. The amendments are not reflected in the instant disclosure. Thus, applicant is asked to review the specification objections and specification amendments made during prosecution of the parent application, and make appropriate corrections.
The disclosure is objected to because of the following informalities:
On page 2, in the first paragraph, insert the patent number of the parent application and use the correct title.
Appropriate correction is required.
Drawings
The drawings are objected to because they are inconsistent with the parent drawings, which were amended to address various objections. The amendments are not reflected in the instant drawings. Thus, applicant is asked to review the drawing objections and drawing amendments made during prosecution of the parent application, and make appropriate corrections.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or amendment to the specification are required in reply to the Office action to avoid abandonment of the application. Please ensure all replacements are in only black and white (as are the originals) to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
Claim 21 is objected to because of the following informalities:
In line 2, insert --and-- after the semicolon.
In the 2nd to last line, insert --to-- after “elements corresponding”.
Applicant is advised that should claim 28 be found allowable, claim 24 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). The examiner recommends deletion of claim 24.
In claim 24, the examiner recommends inserting --processing-- after “array of” for consistency with claim 21.
Claim 25 is objected to because of the following informalities:
In line 7, insert --in-- after “stored”.
Claim 26 is objected to because of the following informalities:
In lines 3-4, replace both instances of “of the” with --corresponding to-- for more consistency with previous language and clearer antecedent basis.
Claim 28 is objected to because of the following informalities:
In line 1, “The apparatus of claim 21” appears twice. Delete the extra instance.
Claims 31 and 34 are objected to because of the following informalities:
These claims make use of both “array of processor elements” and “array of processing elements”. Please amend for consistency.
In claim 31, applicant sets forth “results registers”. Does applicant mean plural results, or --result registers-- instead (e.g. see claim 21 and specification changes made in the parent application)? It is recommended that applicant amend for consistency.
Claim 32 is objected to because of the following informalities:
In line 1, insert --circuitry-- after “logic” for consistency with claim 31.
Claim 33 is objected to because of the following informalities:
In line 2, insert --circuitry-- after “logic” for consistency with claim 31.
Claim 37 is objected to because of the following informalities:
In line 2, insert --and-- after the semicolon.
In line 11, replace “implement” with --implements--.
In lines 15-16, the phrase “from coprocessor instruction received” is grammatically incorrect and must be reworded. Should “instruction” be
--instructions--?
In the 2nd to last line, insert --to-- after “corresponding”.
Claim 39 is objected to because of the following informalities:
In line 7, insert --in-- after “stored”.
Claim 40 is objected to because of the following informalities:
In lines 3-4, replace both instances of “of the” with --corresponding to-- for more consistency with previous language and clearer antecedent basis.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 22, “register rename logic is configured to determine that the storage elements corresponding to the second context are unavailable to the first context when the second context is active”. The only structure set forth for rename logic is a free list, which requires memory (paragraph [0055], last sentence). However, either the free list is not clearly described as performing this function, or the free list is understood to not perform this function. For example, while a free list merely performs the function of storing data, which in this case, may indicate which contexts are active/inactive. Storing data, however, is not necessarily the same as determining that store elements are unavailable. As such, 112(a)/(b) rejections appear below broadest reasonable interpretation (BRI) will be taken.
In claim 23, “the register rename logic is configured to: determine whether any of the plurality of contexts is inactive; and assign storage elements…to an active one of the plurality of contexts”. Again, the free list is memory whose disclosed function is only to store information indicating active/inactive contexts. The free list is not clearly described as performing at least one of these functions, or the free list is understood to not perform at least one of these functions. For example, while a free list may indicate which contexts are active/inactive, this is not necessarily the same as determining whether a context is inactive. Further, the free list alone would seem to be insufficient for assigning storage elements as claimed. As such, 112(a)/(b) rejections appear below and BRI is taken.
In claim 30, “register rename logic…is configured to determine that a corresponding one of the plurality of contexts is inactive”. Again, for similar reasoning given above, the free list memory is understood to only store indications of inactive/active context. The memory itself is not explained as making a determination. It is not clear what register rename structure is actually carrying out the claimed determination. As such, 112(a)/(b) rejections appear below and BRI is taken.
In claim 37, “register rename logic configured to determine which of the plurality of contexts, if any, is active, and further configured to, based on a determination that the second context is inactive, cause the coprocessor to store coprocessor instructions results corresponding to the first context within storage elements corresponding the second context”. For similar reasoning given above, it is not clear how the free list memory would perform such functions. As such, 112(a)/(b) rejections appear below and BRI is taken.
In claim 38, “the register rename logic is further configured to: determine whether any of the plurality of contexts is inactive; determine that the storage elements corresponding to the second context are unavailable to store coprocessor instruction results for the first context when the second context is active; and assign, in response to determining that at least one of the plurality of contexts is inactive, storage elements of at least one inactive one of the plurality of contexts to an active one of the plurality of contexts”. For similar reasoning given above, it is not clear how the free list memory would perform such functions. As such, 112(a)/(b) rejections appear below and BRI is taken.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
At least one claim is identified as including non-limiting contingent limitations. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 33, when there are no inactive contexts, the assigning step is not required. The examiner recommends replacing “whether any” in line 2 with --that at least one-- (and then inserting --the-- after “that” in line 3), which would then cause the method to require the assigning step.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 22-23, 30, and 37-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claims 22-23, 30, and 37-38, the rename logic+function limitations invoke 112(f). As described above, the disclosure does not provide adequate structure to perform the various claimed functions performed by the logic. Thus, the specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. The examiner recommends claiming this logic as a circuit. For instance, in claim 22, applicant could claim “…further comprising a register rename logic circuit”. Per MPEP 2181, “circuit” does not invoke 112(f).
Claims 23 and 38-40 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-23, 26, 30, and 37-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 26, “the storage elements of the second context”, because they could refer to the elements in claim 25 (last paragraph) or claim 21 (last paragraph).
In claim 30, “the results register set”. It appears “results” should be replaced with --result--.
In claim 37, in the 2nd to last paragraph, both instances of “the plurality of processors”. It appears applicant means --the plurality of processor cores--.
In claim 40, “the storage elements of the second context”, because they could refer to the elements in claim 39 (last paragraph) or claim 37 (last paragraph).
Referring to claims 22-23, 30, and 37-38, the rename logic+function limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. That is, as described above, the only structure disclosed is a free list memory. This structure is not clearly disclosed as performing the various functions of these claims. Thus, it is unclear what structure is responsible for performing these functions. When 112(f) is invoked, the structure must be clear. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (again, applicant could instead claim a circuit so as to not invoke 112(f));
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 22-23, 30, and 38-40 are rejected due to their dependence on an indefinite claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 24, 27-31, and 37 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 6, 1, 1, 3, 10, and 16, respectively, of U.S. Patent No. 11,775,301 in view of Stack Overflow (as cited below).
Referring to claim 21, all limitations of claim 21 are anticipated by claim 1 of ‘301 except for “the plurality of contexts including a first context reserved for results from a first one of the plurality of processors and a second context reserved for a second one of the plurality of processors”. However, given that Stack Overflow states that there may be separate contexts for separate cores that offload work to a single GPU, this is an obvious modification to claim 1 of ‘301 so as to dedicate different parts of the GPU to different operations (so one doesn’t interfere with another).
Claims 24 and 28 are anticipated by claim 6 of ‘301.
Claim 27 is anticipated by claims 1 and 9 of ‘301, which set forth an operand register set having multiple registers storing multiple vectors for coprocessor instructions to be executed.
Claim 29 is anticipated by claim 7 of ‘301. Note that a vector instruction operated on vectors, which may also be described as matrices, e.g. a vector with X elements is a 1 row, X column matrix.
Claim 30 is anticipated by claim 3 of ‘301.
Claim 31 is rejected based on claim 10 of ‘301 for similar reasoning that claim 21 is rejected based on claim 1 of ‘301.
Claim 37 is rejected based on claim 16 of ‘301 for similar reasoning that claim 21 is rejected based on claim 1 of ‘301.
Claims 22-23, 32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, respectively, of U.S. Patent No. 11,775,301 in view of Stack Overflow and Chen (as cited below).
Referring to claim 22, while the limitations therein are not taught by claim 1 of ‘301, Chen has taught such limitations in paragraph 153, where registers are only freed if a context is stalled/deadlocked. This means that these registers are not freed (are unavailable to a first context) if the second context is active. This ensures that the second context is not interrupted when actively running to provide more resources to the first context. This realizes fairness between the threads. As a result, it would have been obvious to modify claim 1 of ‘301 to include the limitations of claim 22.
Claim 23 is anticipated by claim 2 of ‘301.
Claim 32 is rejected based on claim 10 of ‘301 for similar reasoning that claim 22 is rejected based on claim 1 of ‘301.
Claims 25-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,775,301 in view of the examiner’s taking of Official Notice.
Referring to claims 25-26, while the limitations therein are not taught by claim 1 of ‘301, they are obvious modifications to claim 1 of ‘301 for reasons set forth below in the prior art rejection of claims 25-26.
Claims 33-36 and 38-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over one or more claims of U.S. Patent No. 11,775,301 in view of one or more of Chen, the examiner’s taking of Official Notice, and Stack Overflow.
Though detailed double patenting rejections for these dependent claims are not set forth herein, the examiner asserts that these claims do not set forth any limitation that is patentably distinct from claims of ‘301, either alone, or as modified according to one of ordinary skill in the art, or according to the cited.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-29 and 31-40 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0096446 (as cited by applicant and herein referred to as Chen)), in view of the examiner’s taking of Official Notice, Stack Overflow (“Can a GPU be shared among multiple cores of a CPU?”), and Tarjan et al. (US 2011/0161616 (as cited by applicant and herein referred to as Tarjan)).
Referring to claim 21, Chen has taught an apparatus comprising:
a plurality of processors configured to execute processor instructions (e.g. FIG.2, processors/cores 202A-N; FIG.10, 1030/1034);
a coprocessor (e.g. FIG.2, 208; FIG.10, 1032; FIG.15; 1514) configured to decode (FIG.15, 1520; paragraph [0144]) and execute coprocessor instructions (execution units 1518 execute coprocessor instructions having the format shown in FIG.7), wherein the coprocessor includes:
an operand register set configured to store operands for coprocessor instructions to be executed (FIG.15, registers 1517);
an array of processing elements (see FIG.6, paragraph [0010], and FIG.15, 1518); and
a result register set comprising storage elements respectively distributed within the array of processing elements (see FIG.17 and the description thereof. Registers are distributed to contexts within the array. Registers are also distributed in the sense that each register is its own physical component in its own physical location in the array), wherein for a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member (any result generated from instruction execution in an execution unit (processing element) will be written to an allocated register (storage element));
wherein the result register set implements a plurality of contexts (see FIG.17 and the description thereof).
While Chen has taught processors/cores (FIG.2, 202) coupled to a coprocessor (FIG.2, 208), and that a CPU works with a GPU (paragraph [0124]), Chen has not explicitly taught wherein ones of the plurality of processors are configured to provide the coprocessor instructions to the coprocessor. However, Official Notice is taken that a processor(s) offloading graphics instructions to a GPU was well known in the art before applicant’s invention. Such an architecture allows a normal processor to offload graphics work, as it is encountered, to a specialized graphics processor for efficient graphics handling, while the normal processor can focus on non-graphics work. By having a processor fetch and filter instructions on behalf of the coprocessor, the coprocessor fetching functionality could be simplified/reduced. In addition, such helps ensure that a processor and coprocessor are not contending for instruction memory at the same time. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that ones of the plurality of processors of Chen are configured to provide the coprocessor instructions to the coprocessor.
Chen has also not taught that the plurality of contexts are configured to store respective coprocessor states corresponding to coprocessor instructions received from different ones of the plurality of processors. However, Stack Overflow has taught that multiple cores can offload respective operations to the same GPU where the GPU would maintain a separate context for each core (see the discussion on p.1). As disclosed, this allows for increased utilization of resources within the GPU, which means fewer unallocated resources and increased parallelism/throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the plurality of contexts are configured to store respective coprocessor states corresponding to coprocessor instructions received from different ones of the plurality of processors.
Chen, as modified, has further taught the plurality of contexts including a first context reserved for results from a first one of the plurality of processors (e.g. FIG.17, CTX#1 and any of the shared registers 1720 associated with CTX#1, which, in the prior art combination, would be reserved for operations from one of the cores) and a second context reserved for a second one of the plurality of processors (e.g. FIG.17, CTX#2 and any of the shared registers 1720 associated with CTX#2, which, in the prior art combination, would be reserved for operations from another of the cores).
Finally, Chen has not explicitly taught wherein, based on a determination that the second context is inactive, the coprocessor is configured to store coprocessor instructions results corresponding to the first context within storage elements corresponding to the second context. The examiner does believe this is generally implied by paragraph [0153], last two sentences, which explain that when a thread is stalled, its context is spilled to allow other threads to make forward progress. Despite this teaching, the examiner asserts that Chen falls short in actually teaching the claim limitation in question. However, Tarjan, in paragraph [0040], explains that when a thread is to be stalled for a long period of time, the context registers for that thread are freed so that they may be used by other threads with expanding footprints. One of ordinary skill in the art understands the benefit of such a technique, where currently-unused registers could be supplied to a second thread to allow the second thread to execute more efficiently. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that, based on a determination that the second context is inactive, the coprocessor is configured to store coprocessor instructions results corresponding to the first context within storage elements corresponding to the second context. As an example, if the thread associated with the second context (CTX#2 and, optionally, shared registers in 1720) is inactive/stalled, CTX#2 registers may be freed and used by the thread assigned to the first context CTX#1.
Referring to claim 22, Chen, as modified, has taught the apparatus of claim 21, further comprising register rename logic (FIG.15, at least 1519), wherein the register rename logic is configured to determine that the storage elements corresponding to the second context are unavailable to the first context when the second context is active (again, in Chen, as modified, storage elements of a second context would only be determined to be available to the first context when the second context is inactive/stalled. Thus, when the second context is determined to be active, the second context registers are not freed, i.e., they are unavailable for the first context. The logic making this determination (and controlling the availability of the second context storage elements) may be considered part of the register rename logic, whose boundaries are not claimed in such a way to preclude this interpretation).
Referring to claim 23, Chen, as modified, has taught the apparatus of claim 22, wherein the register rename logic is configured to:
determine which of the plurality of contexts, if any, is inactive (again, see the last two sentences of Chen (paragraph [0153]) and Tarjan (paragraph [0040]). The rename logic determines a context is inactive (stalled for synchronization purposes)); and
assign storage elements of the result register set corresponding to the inactive context to the active context (again, see the last two sentences of paragraph [0153] and Tarjan. Registers associated with the inactive context are spilled (saved to memory) so that they may be assigned to an active context when it needs additional storage to efficiently make forward progress).
Referring to claim 24, Chen, as modified, has taught the apparatus of claim 21, wherein the array of elements comprises N rows and N columns of processing elements, wherein N is an integer value (see FIG.6. There are two rows and two columns in this array. Even if there are more than two columns, the array comprises two columns).
Referring to claim 25, Chen, as modified, has taught the apparatus of claim 21, wherein the coprocessor is configured to: execute a first coprocessor instruction; and store results of executing the first coprocessor instruction in storage elements corresponding to the first context (the coprocessor will an execute an instruction to write to a register in CTX#1, for instance).
Chen, as modified, has not taught that the coprocessor is configured to begin execution of a second coprocessor instruction prior to completing storing of the results of executing the first coprocessor instruction, wherein results of the second coprocessor instruction are stored storage elements corresponding to the second context, wherein the second coprocessor instruction is associated with the first context. However, Official Notice is taken that pipelined execution which starts executing a subsequent instruction (e.g. in an execution (EX) pipeline stage) before completing storage of a result of a previous instruction (e.g. in a write-back (WB) pipeline stage) was well known in the art before applicant’s invention. This overlap in processing yields increased efficiency and parallelism since the second instruction does not have to wait for the first instruction to finish. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to begin execution of a second coprocessor instruction prior to completing storing of the results of executing the first coprocessor instruction, wherein results of the second coprocessor instruction are stored storage elements corresponding to the second context, wherein the second coprocessor instruction is associated with the first context.
Referring to claim 26, Chen, as modified, has taught the apparatus of claim 25, but has not taught wherein the coprocessor is configured to begin, prior to completing storing of results of the second coprocessor instruction in the storage elements of the second context, a store operation to write back results of executing the first coprocessor instruction from the storage elements of the first context to a system memory. However, Official Notice is taken that a store instruction to store data from a register to system memory was well known in the art before applicant’s invention. This allows data to be stored to a memory accessible by the CPU. For instance, as discussed in Stack Overflow, math operations could be offloaded to the GPU and, if the CPU needs the results of those math operations to take further action, the GPU can store the results of the math from the registers to the system memory where the CPU can access the data. Additionally, for reasoning given above in the rejection of claim 25, it is obvious to pipeline any two given instructions, including the second instruction and a store instruction. This increases parallelism, efficiency, and throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the coprocessor is configured to begin, prior to completing storing of results of the second coprocessor instruction in the storage elements of the second context, a store operation to write back results of executing the first coprocessor instruction from the storage elements of the first context to a system memory.
Referring to claim 27, Chen, as modified, has taught the apparatus of claim 21, wherein the operand register set includes:
a first operand register (FIG.7, 720, paragraphs [0073]-[0074]) configured to store a first vector (see paragraphs [0062] and [0065], where the SIMD instructions can execute on vector data); and a second operand register (FIG.7, 722, paragraphs [0073]-[0074]) configured to store a second vector (again, see paragraphs [0062] and [0065], where the SIMD instructions can execute on vector data); wherein the coprocessor is configured to use the first and second vectors during execution of at least one coprocessor instruction (see FIG.7 and paragraph [0065], where the instruction may be a SIMD instruction that executes on vector sources).
Referring to claim 28, Chen, as modified, has taught the apparatus of claim 21, wherein the array of processing elements comprises N rows and N columns of processing elements, wherein N is an integer value (see FIG.6. There are two rows and two columns in this array. Even if there are more than two columns, the array comprises two columns).
Referring to claim 29, Chen, as modified, has taught the apparatus of claim 28, wherein the coprocessor is configured to:
execute matrix instructions that use at least a subset of the array of processing elements (see paragraph [0065]. With a SIMD instruction, a register stores a matrix of values. Examples given include 1x4 (i.e., one register with four 64-bit elements), 1x8, 1x16, and 1x32 matrices); and
execute vector instructions that use at lease a subset of the array of processing elements (paragraphs [0062] and [0065]).
Claims 31-33 are rejected for similar reasoning as claims 21-23, respectively.
Referring to claim 34, Chen, as modified, has taught the method of claim 31, wherein the array of processing elements comprises N rows and N columns of processing elements, wherein N is an integer value (see FIG.6. There are two rows and two columns in this array. Even if there are more than two columns, the array comprises two columns), and wherein the method further comprises executing coprocessor instructions that use at least a subset of the array of processing elements (since the array of processing elements are what actually carry out the execution of instructions, at least a subset of them are used for such execution).
Claims 35-36 are rejected for similar reasoning as claims 25-26, respectively.
Claim 37 is rejected for similar reasoning as claims 21-23.
Claim 38 is rejected for similar reasoning as claims 22-23.
Claims 39-40 are rejected for similar reasoning as claims 25-26, respectively.
Allowable Subject Matter
Claim 30 is objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record by applicant and not relied upon is considered pertinent to applicant's disclosure:
Levy, 6,092,175, has taught an SSASR scheme (column 10, lines 18-41) where registers corresponding to idle contexts are made available to active contexts.
Levy, 2001/0004755, has taught executing an instruction that would clear a bit in a register to indicate a thread is idle. At this point, its registers are freed and renamed for use by active threads (e.g. see paragraph [0142]).
Gurram, 2020/0004534, has taught a multi-threaded coprocessor that includes a banked register file with groups of registers assigned to each thread (FIGs.16-18).
Serrano, 2019/0294585, has taught donating unused vector register files to a borrower thread which creates a wide vector register file from the donated register files.
Joao, 2018/0276046, has taught reallocating physical registers associated with inactive threads to remaining active threads, and implementing renaming (e.g. paragraph [0031]).
Bybell, 2009/0089817, has taught that when operating in a single thread mode, the single thread may read/write to registers associated with a second thread (e.g. see claims 2-3 and 6-7).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183