DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 2/13/2026 "Reply" elects without traverse and identifies claims 1-7, 9-10, and 12-20 as being drawn to Species B2Z. Accordingly, Examiner has withdrawn claims 8 and 11 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 12/16/2025 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhatia (US Patent No. 5,933,323).
Regarding claim 1, in FIGs. 1-2, Bhatia discloses a chip protection device comprising: a protection frame (210) extending around side surfaces of a semiconductor chip (202) mounted on a substrate (200/201), wherein the protection frame comprises a plurality of side walls (interpreted as at least the leftmost and rightmost walls furthest from the chip), each side wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls (102), each upper wall extending inward from an upper portion of a respective one of the plurality of side walls toward the semiconductor chip; and a plurality of apertures (104) formed through at least some of the plurality of side walls, wherein the plurality of side walls and upper walls define an inner space through which a fluid can flow via the plurality of apertures, and wherein heat from at least some of the side surfaces of the semiconductor chip is transferred to the fluid in the inner space (col. 2, line 61 to col. 3, line 6).
Regarding claim 2, in FIGs. 1-2, Bhatia discloses that the plurality of apertures are horizontally and vertically aligned.
Regarding claim 3, in FIGs. 1-2, Bhatia discloses that each of the plurality of apertures has a circular or rectangular shape (col. 3, lines 40-44).
Regarding claim 4, in FIGs. 1-2, Bhatia discloses that the protection frame further comprises a barrier rib (arbitrary elements 103 not included in apertures) positioned between the side surfaces of the semiconductor chip and the plurality of side walls, and wherein the barrier rib is configured to be parallel to the plurality of upper walls of the protection frame.
Regarding claim 5, in FIGs. 1-2, Bhatia discloses that the protection frame comprises at least one or more of Cu, Al (col. 3, lines 22-30).
Regarding claim 6, in FIGs. 1-2, Bhatia discloses that the protection frame further comprises a plurality of lower walls (101), each lower wall extending inward from a lower portion of a respective one of the plurality of side walls toward the semiconductor chip.
Regarding claim 10, in FIGs. 1-2, Bhatia discloses that the plurality of apertures are arranged in three horizontal rows.
Regarding claim 12, in FIGs. 1-2, Bhatia discloses that the plurality of upper walls of the protection frame are coplanar with an upper surface of the semiconductor chip.
Regarding claim 13, in FIGs. 1-2, Bhatia discloses that the plurality of apertures are formed in two side walls of the protection frame that are opposite each other.
Regarding claim 14, in FIGs. 1-2, Bhatia discloses that the plurality of apertures are formed in each of the plurality of side walls.
Allowable Subject Matter
Claims 7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 15-18, in FIGs. 1-2, Bhatia discloses a chip protection device comprising: a protection frame (210) extending around side surfaces of a semiconductor chip (201) mounted on a substrate (200/201), wherein the protection frame comprises a plurality of side walls (interpreted as at least the leftmost and rightmost walls furthest from the chip), each side wall facing and spaced apart from a respective side surface of the semiconductor chip, a plurality of upper walls (102), each upper wall extending inward from an upper portion of a respective one of the plurality of side walls toward the semiconductor chip, and a plurality of lower walls (101), each lower wall extending inward from a lower portion of a respective one of the plurality of side walls toward the semiconductor chip; and a plurality of apertures (104) formed through at least some of the plurality of side walls, wherein the plurality of side walls, the plurality of upper walls, and the plurality of lower walls define an inner space through which a fluid can flow via the plurality of apertures (col. 2, line 61 to col. 3, line 6); and wherein heat from at least some of the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.
However, the prior art failed to disclose or reasonably suggest the claimed chip protection device particularly characterized by a portion of at least one of the plurality of upper walls contacts a respective side surface of the semiconductor chip, and wherein a portion of at least one of the plurality of lower walls contacts a respective side surface of the semiconductor chip.
Regarding claims 19-20, in FIGs. 1-2, Bhatia discloses a chip protection device comprising: a protection frame (210) extending around side surfaces of a semiconductor chip (202) mounted on a substrate (201/200), wherein the protection frame comprises a plurality of side walls (interpreted as at least the leftmost and rightmost walls furthest from the chip), each side wall facing and spaced apart from a respective side surface of the semiconductor chip, a plurality of upper walls (102), each upper wall extending inward from an upper portion of a respective one of the plurality of side walls toward the semiconductor chip, and a plurality of lower walls (101), each lower wall extending inward from a lower portion of a respective one of the plurality of side walls toward the semiconductor chip; and a plurality of apertures (104) formed through at least some of the plurality of side walls, wherein the plurality of apertures are aligned horizontally and vertically, wherein the plurality of side walls, the plurality of upper walls, and the plurality of lower walls define an inner space through which a fluid can flow via the plurality of apertures (col. 2, line 61 to col. 3, line 6), and wherein heat from at least some of the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.
However, the prior art failed to disclose or reasonably suggest the claimed chip protection device particularly characterized by a portion of at least one of the plurality of upper walls contacts a respective side surface of the semiconductor chip, and wherein a portion of at least one of the plurality of lower walls contacts a respective side surface of the semiconductor chip.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891