DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is a response to the restriction requirement filed on 6/15/2026.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-6, in the reply filed on 6/15/2026 is acknowledged.
Claims 7-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/15/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --METHOD FOR MANUFACTURING A HIGH-HEAT-DISSIPATION MIXED SUBSTRATE--.
Claim Objections
Claims 2-5 are objected to because of the following informalities:
Re. claim 2: The phrase “wherein the filling the first groove with a thermally-conductive material to form a first thermally- conductive block comprises” as recited in lines 2-3 appears to be --wherein the filling the first groove with the thermally-conductive material to form the first thermally- conductive block comprises--.
Re. claim 3: The phrase “to obtain a target mother substrate” as recited in line 3 appears to be --to obtain the target mother substrate--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (PGPub 2014/0151104 A1) in view of Hurwitz et al. (PGPub 2015/0279814 A1).
Chung et al. teach a process of making a high-heat-dissipation mixed substrate, comprising steps of: preparing a mother substrate (110, Fig. 5B, paragraph [0121]), wherein the mother substrate comprises an insulating layer and a temporary carrier plate (DF, Fig. 5D, paragraph [0126]), the insulating layer and the temporary carrier plate are laminated with each other; arranging a plurality of first grooves and a plurality of first cavities (111, Fig. 5B, paragraph [0121]), on the mother substrate, wherein the mother substrate comprises a plurality of sub-substrates and region dividing lines, and the sub-substrate comprises at least one of the first cavities, the first groove is arranged to extend across two adjacent sub-substrates as shown in Fig. 5B, the region dividing lines are configured to divide a projection pattern of the first groove in a direction perpendicular to the mother substrate into two parts, and the first groove and the first cavity both extend through the insulating layer in the direction perpendicular to the mother substrate as shown in Fig. 5B; filling the first groove with a thermally-conductive material (VT, Fig. 5C, paragraph [0124]) to form a first thermally-conductive block, and adhering an embedded device (161, 162, Fig. 5E, paragraph [0126]) in the first cavity and filling the first cavity with the thermally-conductive material (150, Fig. 5F, paragraph [0127]) to form a second thermally-conductive block; removing the temporary carrier plate to obtain a semi-finished substrate as shown in Fig. 5H, paragraph [0130]); and manufacturing circuit layers (181, 182, Fig. 5I, paragraph [01131]) on two opposite side surfaces of the semi-finished substrate to obtain a target mother substrate.
However, Chung et al. fail to teach a process of cutting the target mother substrate along the region dividing lines to obtain a mixed substrate with a side surface being a thermally-conductive surface. Hurwitz et al. teach a process of making an embedded chip including a process of cutting a substrate along the region dividing lines to obtain an individual substrate with a side surface being a thermally-conductive surface as shown in Figs. 4 and 5 (paragraphs [0098]-[0099]). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating a high-heat-dissipation mixed substrate of Chung et al. by cutting the substrate along the region dividing lines to obtain a substrate with a side surface being a thermally-conductive surface as taught by Hurwitz et al. in order to produce a plurality individual of high-heat-dissipation mixed substrates.
Re. claim 3: Chung et al. also teach the manufacturing circuit layers on two opposite side surfaces of the semi-finished substrate to obtain a target mother substrate , comprising steps of: manufacturing a first via (V1-V6) for connection between a first circuit layer (120, Fig. 5A) and a second circuit layer (130, Fig. 5A) on the two side surfaces of the semi-finished substrate; manufacturing the first circuit layer on one side surface of the semi-finished substrate, and manufacturing a third circuit layer (181, Fig. 5I) connected with the first circuit layer; and manufacturing the second circuit layer on the other side surface opposite to the one side surface of the semi-finished substrate, and manufacturing a fourth circuit layer (182, Fig. 5I) connected with the second circuit layer.
Re. claim 6: : Chung et al. also teach that the embedded device is a semiconductor chip.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. in view of Hurwitz et al. as applied to claim 1 above, and further in view of Hsien (US PAT. 6,976,306).
Chung et al., modified by Hurwitz et al., teach all limitations as set forth above, but silent a screen printing with the thermally-conductive material for filling the first groove to form the first thermally-conductive block. Hsien teaches a process of making a circuit board including a process of silk screen printing for filling vias a conductive material (250) to allow stack via (blind vias stack on the buried vias) and increase the electric conduction reliability between new built-up layers as shown in Figs. 2D-2E (col. 2, lines 27-30). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating a high-heat-dissipation mixed substrate of Chung et al., modified by Hurwitz et al., by a screen printing with the thermally-conductive material for filling the groove as taught by Hsien in order to increase the electric conduction reliability between new built-up layers.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. in view of Hurwitz et al. as applied to claim 1 above, and further in view of Gowda et al. (US PAT. 9,953,913).
Chung et al., modified by Hurwitz et al., teach all limitations as set forth above, but silent how to make the first circuit layer on one side surface of the semi-finished substrate. Gowda et al. teach a process of making an electronic package including a process of manufacturing a first metal seed layer; laminating a photoresist material (such as a photoresist mask) on the first metal seed layer (104); and exposing, developing the photoresist material, and performing an etching process to obtain the patterned conductive layer as shown in Fig. 19 (col. 12, lines 53-66). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating a high-heat-dissipation mixed substrate of Chung et al., modified by Hurwitz et al., by manufacturing the first circuit layer on one side surface of the semi-finished substrate as taught by Gowda et al. in order to produce a desired conductive pattern for the first circuit layer on one side surface of the semi-finished substrate.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. in view of Hurwitz et al. as applied to claim 1 above, and further in view of Hurwitz et al. (US PAT. 9,911,700).
Chung et al., modified by Hurwitz et al., teach all limitations as set forth above, but silent the thermally-conductive material. Hurwitz et al. teach a process of making an embedded package using a package material such that “the die terminal face contains metal terminal contacts surrounded by a dielectric passivation layer where said metal terminal contacts and said dielectric passivation layer are coplanar with the first frame face and a face of the intervening packaging material… the passivation layer is selected from the group comprising polyimides and silicon nitride” (col. 4, lines 4-13). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating a high-heat-dissipation mixed substrate of Chung et al., modified by Hurwitz et al., by providing the thermally-conductive material as taught by Hurwitz et al. in order to produce the well-known benefit of obtaining a desired high-heat-dissipation mixed substrate. In addition, one of ordinary skill in the art could easily select materials from the recited lists to result in the required differing compositions. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The applicant has not disclosed any criticality for the claimed limitations.
Conclusion
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/PAUL D KIM/Primary Examiner, Art Unit 3729
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