DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 11 – 13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 12,279,452 to Cheng et al.
Regarding claim 1, Cheng et al. teach a semiconductor device (Fig. 1), comprising:
a first source/drain region (160-2);
a first contact (192) over the first source/drain region, wherein portions of the first contact are recessed (Contact is recessed in the insulation layers 175 and 176);
a second source/drain region (162-2); and
a lateral contact (200) connecting the second source/drain region to a back end of line (BEOL) (Col. 8, lines 12 – 14), wherein the lateral contact overlaps with the recessed portions of the first contact, and wherein the first source/drain region is formed over the second source/drain region.
Regarding claim 2, Cheng et al. teach a semiconductor device, wherein the lateral contact is located above the first and second source/drain regions. See Fig. 1.
Regarding claim 3, Cheng et al. teach a semiconductor device, wherein the first source/drain region is located on a first transistor (101) and the second source/drain region is located on a second transistor (102), and wherein the first transistor is stacked over the second transistor. See Fig. 1.
Regarding claim 5, Cheng et al. teach a semiconductor device, further comprising: a gate contact (190) connecting a gate region to the BEOL; and
a dielectric isolation layer (176) covering the gate contact.
Regarding claim 11, Cheng et al. teach a method for forming a semiconductor device, the method comprising:
forming a first source/drain region (160-2);
forming a first contact (192) over the first source/drain region, wherein portions of the first contact are recessed (Contact is recessed in the dielectric layers 176 and 175);
forming a second source/drain region (162-2); and
forming a lateral contact (200) connecting the second source/drain region to a back end of line (BEOL), wherein the lateral contact overlaps with the recessed portions of the first contact, and wherein the first source/drain region is formed over the second source/drain region. See Fig. 1.
Regarding claim 12, Cheng et al. teach a method, wherein the lateral contact is located above the first and second source/drain regions. See Fig. 1.
Regarding claim 13, Cheng et al. teach a method, wherein the first source/drain region is located on a first transistor (101) and the second source/drain region is located on a second transistor (102), and wherein the first transistor is stacked over the second transistor.
Regarding claim 15, Cheng et al. teach a method, further comprising: forming a gate contact (190) connecting a gate region to the BEOL; and forming a dielectric isolation layer (176) covering the gate contact.
Allowable Subject Matter
Claim 20 is allowed.
Claims 4, 6 – 10, 14, and 16 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or reasonably suggest a semiconductor device as recited in claim 20, including “a lateral contact, wherein the gate contact is isolated from direct contact with the lateral contact through a dielectric isolation layer formed over the gate contact.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2022/0238713 to Lee et al. teach a semiconductor device including a recessed contact to a BEOL structure. Lee et al. do not teach a lateral contact connecting a second source/drain region to a BEOL.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897