DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-25) in the reply filed on 12/19/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 17, 20, and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (U.S. Publication No. 20200365715 A1)
With respect to claim 1, Yoshida discloses a semiconductor device including a transistor portion [70] and a diode portion [80], comprising: a drift region [18] of a first conductivity type [N-type], which is provided in a semiconductor substrate [10]; a collector region [22] of a second conductivity type [P-type], which is provided on a back surface of the semiconductor substrate; a cathode region [82] of the first conductivity type, which is provided on the back surface of the semiconductor substrate and has a higher doping concentration than the drift region (see Figure 3; N+ cathode vs N- drift); a plurality of trench portions [30/40] provided on a front surface of the semiconductor substrate; and a lifetime control portion [141/142] which is provided in the semiconductor substrate and contains a lifetime killer (see ¶[0090]; crystal defect), wherein the lifetime control portion includes: a main region [141] provided in the diode portion; and a decay region [142] which is provided to extend from the main region in a direction parallel to the front surface of the semiconductor substrate and has a lifetime killer concentration that has decayed more than a lifetime killer concentration of the main region (See Figure 3 and ¶[0090]; “shortened by a recombination of a carrier with a crystal defect or the like”).
With respect to claim 2, Yoshida discloses wherein the decay region is provided to extend from the main region in the direction parallel to the front surface of the semiconductor substrate in the diode portion (see Figure 3).
With respect to claim 3, Yoshida discloses wherein the decay region extends from the main region to a boundary between the collector region and the cathode region in a top view (see Figure 3).
With respect to claim 4, Yoshida discloses wherein the decay region extends from the main region to an inside of the collector region beyond a boundary between the collector region and the cathode region in a top view (See Figure 3).
With respect to claim 5, Yoshida discloses wherein the main region extends from an inside of the cathode region to a boundary between the collector region and the cathode region in a top view, and the decay region extends from the boundary between the collector region and the cathode region to an inside of the collector region in the top view (see Figure 3).
With respect to claim 6, Yoshida discloses wherein the main region extends from an inside of the cathode region in the direction parallel to the front surface of the semiconductor substrate, and is terminated without extending to a boundary between the collector region and the cathode region in a top view, and the decay region extends from the main region to an inside of the collector region beyond the boundary between the collector region and the cathode region in the top view (see Figure 3).
With respect to claim 7, Yoshida discloses wherein the main region extends from an inside of the cathode region in the direction parallel to the front surface of the semiconductor substrate, and is terminated without extending to a boundary between the collector region and the cathode region in a top view, and the decay region extends from the main region to the boundary between the collector region and the cathode region in the direction parallel to the front surface of the semiconductor substrate, and is terminated at the boundary in the top view (see Figure 3).
With respect to claim 8, Yoshida discloses a semiconductor device including a transistor portion [70] and a diode portion [80], comprising: a drift region [18] of a first conductivity type [N-type], which is provided in a semiconductor substrate [10]; a collector region [22] of a second conductivity type [P-type], which is provided on a back surface of the semiconductor substrate; a cathode region [82] of the first conductivity type, which is provided on the back surface of the semiconductor substrate and has a higher doping concentration than the drift region (see Figure 3; N+ cathode vs N- drift); a plurality of trench portions [30/40] provided on a front surface of the semiconductor substrate; and a lifetime control portion [141] which is provided in the semiconductor substrate and contains a lifetime killer (see ¶[0090]; crystal defect), wherein the lifetime control portion extends from an inside of the cathode region in a direction parallel to the front surface of the semiconductor substrate, and is terminated without extending to a boundary between the collector region and the cathode region in a top view (See Figure 3).
With respect to claim 9, Yoshida discloses wherein the lifetime control portion includes: a main region provided in the diode portion; and a decay region which is provided to extend from the main region in the direction parallel to the front surface of the semiconductor substrate and has a lifetime killer concentration that has decayed more than a lifetime killer concentration of the main region, the main region extends from the inside of the cathode region in the direction parallel to the front surface of the semiconductor substrate, and is terminated without extending to the boundary between the collector region and the cathode region in the top view, and the decay region extends from the main region in the direction parallel to the front surface of the semiconductor substrate, and is terminated without extending to the boundary between the collector region and the cathode region in the top view (see Figure 3; ¶[0090]).
With respect to claim 17, Yoshida discloses wherein the lifetime control portion contains helium (See ¶[0012]).
With respect to claim 20, Yoshida discloses wherein the main region occupies 80% or more of a width of the diode portion in a trench array direction (see Figure 3).
With respect to claim 23, Yoshida discloses wherein the main region has a uniform doping concentration in the direction parallel to the front surface of the semiconductor substrate (see ¶[0033]).
With respect to claim 24, Yoshida discloses wherein the transistor portion includes a boundary region [72] provided in direct contact with the diode portion, and the boundary region includes a base region [14] of the second conductivity type on the front surface (see Figure 3).
With respect to claim 25, Yoshida discloses wherein the transistor portion includes a boundary region [72] provided in direct contact with the diode portion, and the boundary region includes a contact region [17] of the second conductivity type, which has a higher doping concentration than a base region [14] of the second conductivity type provided on the front surface (see ¶[0076]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kubouchi (U.S. Publication No. 2020/0357903 A1)
With respect to claim 10, Yoshida fails to explicitly disclose wherein the lifetime control portion is a front surface side lifetime control region provided closer to the front surface than a center of the semiconductor substrate in a depth direction In the same field of endeavor, Kubouchi teaches the lifetime control portion [72] is a front surface side lifetime control region provided closer to the front surface than a center of the semiconductor substrate in a depth direction (see Figure 6C and ¶[0124]). Implementation of a lifetime control region closer to the front surface than a center of the semiconductor substrate as taught by Kubouchi allows for reverse recovery loss reduction (see ¶[0125]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 11, the combination of Yoshida and Kubouchi discloses the lifetime control portion includes a back surface side lifetime control region [73] which is provided closer to the back surface than the center of the semiconductor substrate in the depth direction and is provided across an entire surface of the semiconductor substrate (See Kubouchi Figure 6C ¶[0169]). Implementation of a back surface side lifetime control region as taught by Kubouchi allows for some of carriers drifting in the drift region to be recombined and disappear within the two lifetime control regions and can adjust the lifetime of the carriers implanted by adjusting the depth of the lifetime control region from the lower surface (see ¶[0171]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, Yoshida fails to disclose discloses wherein the lifetime control portion is a back surface side lifetime control region provided closer to the back surface of the semiconductor substrate than a center of the semiconductor substrate in a depth direction. In the same field of endeavor, Kubouchi teaches wherein the lifetime control portion [73] is a back surface side lifetime control region provided closer to the back surface of the semiconductor substrate than a center of the semiconductor substrate in a depth direction (See Kubouchi Figure 6C ¶[0169]). Implementation of a back surface side lifetime control region as taught by Kubouchi allows for some of carriers drifting in the drift region to be recombined and disappear within the two lifetime control regions and can adjust the lifetime of the carriers implanted by adjusting the depth of the lifetime control region from the lower surface (see ¶[0171]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 13, the combination of Yoshida and Kubouchi discloses comprising: a buffer region [20] of the first conductivity type, which is provided closer to the back surface of the semiconductor substrate than the center of the semiconductor substrate in the depth direction, wherein the buffer region has one or more peaks of a doping concentration in the depth direction of the semiconductor substrate (See Kubouchi ¶[0202] and ¶[0284]).
With respect to claim 14, the combination of Yoshida and Kubouchi discloses wherein the one or more peaks contain a hydrogen donor (see ¶[0022]).
With respect to claim 15, the combination of Yoshida and Kubouchi discloses wherein the buffer region has four peaks of the doping concentration in the depth direction of the semiconductor substrate, and the lifetime control portion is provided between a second peak second closest to the back surface of the semiconductor substrate and a third peak third closest to the back surface out of the four peaks in the depth direction of the semiconductor substrate (See Kubouchi Figures 30-31; depth control to allow particles of helium to penetrate the buffer material multiple times along the length of [72]).
With respect to claim 16, the combination of Yoshida and Kubouchi fails to explicitly disclose wherein the lifetime control portion has a peak of the lifetime killer concentration at a position that is 10 μm or more and 15 μm or less from the back surface of the semiconductor substrate in the depth direction of the semiconductor substrate, however does disclose depth of implantation control within the device (See Kubouchi ¶[0290-0297]). It has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to determine the optimal position of peak lifetime killer concentration based on routine experimentation to allow for some of carriers drifting in the drift region to be recombined and disappear within the two lifetime control regions and can adjust the lifetime of the carriers implanted by adjusting the depth of the lifetime control region from the lower surface (see ¶[0171]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida
With respect to claim 21, Yoshida fails to explicitly disclose wherein a width of the decay region is 0.1 μm or more and 10.0 μm or less in a trench array direction, however does disclose a decay region (See Figure 3). It has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to determine the optimal position of the decay region based on routine experimentation to suppress a hole injection from the transistor section to the diode section (See ¶[0090]).
Allowable Subject Matter
Claims 18-19 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 18, none of the prior art teaches or suggests, alone or in combination, wherein the main region is sandwiched between decay regions including the decay region in a trench array direction.
With respect to claim 19, none of the prior art teaches or suggests, alone or in combination, wherein the main region is enclosed by the decay region in the direction parallel to the front surface of the semiconductor substrate.
With respect to claim 22, none of the prior art teaches or suggests, alone or in combination, wherein a width of the decay region is a diffusion half width at half maximum by which a lifetime killer for forming the main region is diffused.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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