Prosecution Insights
Last updated: April 19, 2026
Application No. 18/453,341

SEMICONDUCTOR MODULE

Non-Final OA §102
Filed
Aug 22, 2023
Examiner
PROSTOR, ANDREW VICTOR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
3y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
24 granted / 25 resolved
+28.0% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
27 currently pending
Career history
52
Total Applications
across all art units

Statute-Specific Performance

§103
48.0%
+8.0% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-29 are pending. Claims 1, 2, 4, 7-14, 16-17, 19, and 22-28 are elected without traverse. Note to applicant, claims 8-9, and 23 are dependent on non-elected claims 6 and 21 respectively, and are therefore also considered non-elected. Claims 3, 5-6, 8-9, 15, 18, 20-21, 23, and 29 are withdrawn from consideration. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the upper arm, lower arm, and plurality of legs must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. For the purposes of examination, the upper arm will be interpreted as meaning the upper half of the semiconductor device, the lower arm will be interpreted as meaning the lower half of the semiconductor device, and the plurality of legs will be interpreted as meaning the sealing resin below the leadframe/substrate. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4, 7, 10-14, 16-17, 19, 22, and 24-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0371921 A1 Tanaka (herein “Tanaka”). Regarding Claim 1, Tanaka discloses: A semiconductor module (see Figs. 1 (1a and 1b top down and profile views) and 2 (circuit diagram) comprising: a reverse conducting first switching element (#2, includes #2a and #2b) which is provided on one of an upper arm (top portion) and a lower arm (bottom portion); a reverse conducting second switching element (#2, includes #2a and #2b) which is provided on another of the upper arm (upper portion) and the lower arm (lower portion); a first path member (see annotated Fig. 1 below) which is electrically connected to one of a gate electrode (#2b) and an emitter electrode (#2a) of the first switching element (#2); and a second path member (see annotated Fig. 1 below) which is electrically connected to another of the gate electrode (#2b) and the emitter electrode (#2a) of the first switching element (#2), wherein the first path member (see annotated Fig. 1 below) is provided to be closer (first path member is closer to top switching element than bottom path member) to the second switching element (#2) than the second path member (see annotated Fig. 1 below), current flowing through the first path member flows in antiparallel with a reverse recovery current of an arm provided with the second switching element (see [0031]: “The bonding wire 3a connecting the IGBT 2a and the FWD 2b is, for example, an aluminum wire having a diameter of about 400 μm. Ordinarily, the surface electrode of the IGBT 2a acts as an emitter while the surface electrode of the FWD 2b acts as an anode. This connects the IGBT 2a and the FWD 2b in anti-parallel.”, see additional note below), and the first path member (see annotated Fig. 1 below), the first switching element (#2), and the second switching element (#2) are arranged on a same insulating substrate (#1, see Fig. 1(b)). Note, see [0037]: “FIG. 2 is an electric circuit diagram of the illustrated structure according to the first embodiment of the present invention. Two pairs of the IGBTs 2a and FWDs 2b are connected in series. The electric circuit diagram in FIG. 2 illustrates an inverter of one arm. The FWDs 2b are connected in anti-parallel so as to allow a reverse recovery current generated by an overvoltage during switching of the IGBTs 2a to pass through the FWDs 2b, thereby preventing the IGBTs 2a from being broken. For example, an inverter circuit for a three-phase alternating current can be formed by combining three semiconductor devices with such a circuit configuration. The inverter circuit can be used for, for example, controlling the rotation of a motor.”, emphasis added. PNG media_image1.png 642 934 media_image1.png Greyscale Tanaka Fig. 1 – Annotated by Examiner Regarding Claim 2, Tanaka discloses: The semiconductor module according to claim 1, wherein the first path member (see annotated Fig. 1 above) is a gate wiring member electrically connected to the gate electrode (see [0031]: “Furthermore, a gate electrode is provided on the surface of the IGBT 2a in addition to the emitter. The gate electrode and the lead frame 1 are connected via the bonding wire 3b.”) of the first switching element (#2), and the second path member (see annotated Fig. 1 above) is an auxiliary emitter wiring member () electrically connected to the emitter electrode (see [0031]: “Ordinarily, the surface electrode of the IGBT 2a acts as an emitter while the surface electrode of the FWD 2b acts as an anode.”) of the first switching element (#2). Regarding Claim 4, Tanaka discloses: The semiconductor module according to claim 1, wherein the first path member and the second path member have a conductive circuit board (see annotated Fig. 1 above), and the circuit board of the first path member is provided between the circuit board of the second path member and the second switching element in a top view (see annotated Fig. 1 above, second path member and second switching element surround first path member). Regarding Claim 7, Tanaka discloses: The semiconductor module according to claim 1, comprising: a gate external terminal (#8) which is electrically connected to the gate electrode of the first switching element (#2) via the first path member (see annotated Fig. 1 above) or the second path member (see annotated Fig. 1 above); and an auxiliary emitter external terminal (#8) which is electrically connected to the emitter electrode of the first switching element (#2) via the first path member (see annotated Fig. 1 above) or the second path member (see annotated Fig. 1 above), wherein the gate external terminal is provided to be farther from the second switching element than the auxiliary emitter external terminal (see annotated Fig. 1 above). Regarding Claim 10, Tanaka discloses: The semiconductor module according to claim 1, wherein each of the first switching element (#2, top) and the second switching element (#2, bottom) is constituted by one chip (mounted on leadframe #1, see Fig. 2). Regarding Claim 11, Tanaka discloses: The semiconductor module according to claim 10, wherein the first switching element and the second switching element are any one of an RC-IGBT, an element in which a SiC-MOS and a SiC-SBD are integrated, or an element in which a body diode of the SiC-MOS is caused to function as a freewheeling diode (see paragraph [0031]). Regarding Claim 12, Tanaka discloses: The semiconductor module according to claim 1, wherein a gate wiring member electrically connected to the gate electrode of the first switching element is longer than a gate wiring member electrically connected to a gate electrode of the second switching element (see below). Note, Tanaka discloses gate wiring members connected to gate electrodes of first and second switching elements are equal in length, see Fig. 1, however, MPEP 2144.04 IV states changes in size/proportion/shape do not render a claim patentably distinct from the cited prior art. In this case, the length of the wire connecting gate electrodes would not function/perform differently with different lengths of wires, and as previously disclosed above, the claimed device is functionally identical to the prior art, therefore the claimed limitation, specifically in regards to the length of wires connecting respective gate electrodes is not patentably distinct over the prior art of record. “MPEP 2144.04 IV A: In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package “of appreciable size and weight requiring handling by a lift truck” were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) (“mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled.” 531 F.2d at 1053, 189 USPQ at 148.). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.” Regarding Claim 13, Tanaka discloses: The semiconductor module according to claim 1, wherein an auxiliary emitter wiring member electrically connected to the emitter electrode of the first switching element is longer than an auxiliary emitter wiring member electrically connected to an emitter electrode of the second switching element. Note, Tanaka discloses auxiliary wiring members connected to emitter electrodes of first and second switching elements are equal in length, see Fig. 1, however, MPEP 2144.04 IV states changes in size/proportion/shape do not render a claim patentably distinct from the cited prior art. In this case, the length of the wire connecting emitter electrodes would not function/perform differently with different lengths of wires, and as previously disclosed above, the claimed device is functionally identical to the prior art, therefore the claimed limitation, specifically in regards to the length of wires connecting respective gate electrodes is not patentably distinct over the prior art of record. “MPEP 2144.04 IV A: In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package “of appreciable size and weight requiring handling by a lift truck” were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) (“mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled.” 531 F.2d at 1053, 189 USPQ at 148.). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.” Regarding Claim 14, Tanaka discloses: The semiconductor module according to claim 1, comprising: a plurality of legs (#10, Fig. 2), each of which is constituted by an upper arm and a lower arm (see annotated Fig. 1 above); and a plurality of laminated substrates (#1, [0031], laminated by #4) for arranging the plurality of legs, wherein the plurality of legs are arranged on the plurality of laminated substrates, respectively. See drawings objection above. Regarding Claim 16, Tanaka discloses: A semiconductor module (see Figs. 1 (1a and 1b top down and profile views) and 2 (circuit diagram) comprising: a reverse conducting first switching element (#2, includes #2a and #2b) which is provided on one of an upper arm (top portion) and a lower arm (bottom portion); a reverse conducting second switching element (#2, includes #2a and #2b) which is provided on another of the upper arm (upper portion) and the lower arm (lower portion); a first path member (see annotated Fig. 1 below) which is electrically connected to one of a gate electrode (#2b) and an emitter electrode (#2a) of the first switching element (#2); and a second path member (see annotated Fig. 1 below) which is electrically connected to another of the gate electrode (#2b) and the emitter electrode (#2a) of the first switching element (#2), a gate external terminal (#8) which is electrically connected to the gate electrode of the first switching element (#2) via one of the first path member (see annotated Fig. 1 above) and the second path member (see annotated Fig. 1 above); an auxiliary emitter external terminal (#8) which is electrically connected to the emitter electrode of the first switching element (#2) via another of the first path member (see annotated Fig. 1 above) and the second path member (see annotated Fig. 1 above), wherein a positive electrode terminal (#5) and a negative electrode terminal (#6) which are provided on one predetermined side of the semiconductor module (left side of Fig. 1), wherein the first path member (see annotated Fig. 1 below) is provided to be closer (first path member is closer to top switching element than bottom path member) to the second switching element (#2) than the second path member (see annotated Fig. 1 below), current flowing through the first path member flows in antiparallel with a reverse recovery current of an arm provided with the second switching element (see [0031]: “The bonding wire 3a connecting the IGBT 2a and the FWD 2b is, for example, an aluminum wire having a diameter of about 400 μm. Ordinarily, the surface electrode of the IGBT 2a acts as an emitter while the surface electrode of the FWD 2b acts as an anode. This connects the IGBT 2a and the FWD 2b in anti-parallel.”, see additional note below), and and the positive electrode terminal (#5) and the negative electrode terminal (#6) are provided on a side orthogonal to a side on which the gate external terminal (#8) and the auxiliary emitter external terminal (#8) are provided. Note, see [0037]: “FIG. 2 is an electric circuit diagram of the illustrated structure according to the first embodiment of the present invention. Two pairs of the IGBTs 2a and FWDs 2b are connected in series. The electric circuit diagram in FIG. 2 illustrates an inverter of one arm. The FWDs 2b are connected in anti-parallel so as to allow a reverse recovery current generated by an overvoltage during switching of the IGBTs 2a to pass through the FWDs 2b, thereby preventing the IGBTs 2a from being broken. For example, an inverter circuit for a three-phase alternating current can be formed by combining three semiconductor devices with such a circuit configuration. The inverter circuit can be used for, for example, controlling the rotation of a motor.”, emphasis added. PNG media_image1.png 642 934 media_image1.png Greyscale Tanaka Fig. 1 – Annotated by Examiner Regarding Claim 17, Tanaka discloses: The semiconductor module according to claim 16, wherein the first path member (see annotated Fig. 1 above) is a gate wiring member electrically connected to the gate electrode (see [0031]: “Furthermore, a gate electrode is provided on the surface of the IGBT 2a in addition to the emitter. The gate electrode and the lead frame 1 are connected via the bonding wire 3b.”) of the first switching element (#2), and the second path member (see annotated Fig. 1 above) is an auxiliary emitter wiring member () electrically connected to the emitter electrode (see [0031]: “Ordinarily, the surface electrode of the IGBT 2a acts as an emitter while the surface electrode of the FWD 2b acts as an anode.”) of the first switching element (#2). Regarding Claim 19, Tanaka discloses: The semiconductor module according to claim 16, wherein the first path member and the second path member have a conductive circuit board (see annotated Fig. 1 above), and the circuit board of the first path member is provided between the circuit board of the second path member and the second switching element in a top view (see annotated Fig. 1 above, second path member and second switching element surround first path member). Regarding Claim 22, Tanaka discloses: The semiconductor module according to claim 16, wherein the gate external terminal is provided to be farther from the second switching element than the auxiliary emitter external terminal (see annotated Fig. 1 above). Regarding Claim 24, Tanaka discloses: The semiconductor module according to claim 16, wherein each of the first switching element (#2, top) and the second switching element (#2, bottom) is constituted by one chip (mounted on leadframe #1, see Fig. 2). Regarding Claim 25, Tanaka discloses: The semiconductor module according to claim 24, wherein the first switching element and the second switching element are any one of an RC-IGBT, an element in which a SiC-MOS and a SiC-SBD are integrated, or an element in which a body diode of the SiC-MOS is caused to function as a freewheeling diode (see paragraph [0031]). Regarding Claim 26, Tanaka discloses: The semiconductor module according to claim 16, wherein a gate wiring member electrically connected to the gate electrode of the first switching element is longer than a gate wiring member electrically connected to a gate electrode of the second switching element (see below). Note, Tanaka discloses gate wiring members connected to gate electrodes of first and second switching elements are equal in length, see Fig. 1, however, MPEP 2144.04 IV states changes in size/proportion/shape do not render a claim patentably distinct from the cited prior art. In this case, the length of the wire connecting gate electrodes would not function/perform differently with different lengths of wires, and as previously disclosed above, the claimed device is functionally identical to the prior art, therefore the claimed limitation, specifically in regards to the length of wires connecting respective gate electrodes is not patentably distinct over the prior art of record. “MPEP 2144.04 IV A: In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package “of appreciable size and weight requiring handling by a lift truck” were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) (“mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled.” 531 F.2d at 1053, 189 USPQ at 148.). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.” Regarding Claim 27, Tanaka discloses: The semiconductor module according to claim 16, wherein an auxiliary emitter wiring member electrically connected to the emitter electrode of the first switching element is longer than an auxiliary emitter wiring member electrically connected to an emitter electrode of the second switching element. Note, Tanaka discloses auxiliary wiring members connected to emitter electrodes of first and second switching elements are equal in length, see Fig. 1, however, MPEP 2144.04 IV states changes in size/proportion/shape do not render a claim patentably distinct from the cited prior art. In this case, the length of the wire connecting emitter electrodes would not function/perform differently with different lengths of wires, and as previously disclosed above, the claimed device is functionally identical to the prior art, therefore the claimed limitation, specifically in regards to the length of wires connecting respective gate electrodes is not patentably distinct over the prior art of record. “MPEP 2144.04 IV A: In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package “of appreciable size and weight requiring handling by a lift truck” were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) (“mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled.” 531 F.2d at 1053, 189 USPQ at 148.). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.” Regarding Claim 28, Tanaka discloses: The semiconductor module according to claim 16, comprising: a plurality of legs (#10, Fig. 2), each of which is constituted by an upper arm and a lower arm (see annotated Fig. 1 above); and a plurality of laminated substrates (#1, [0031], laminated by #4) for arranging the plurality of legs, wherein the plurality of legs are arranged on the plurality of laminated substrates, respectively. See drawings objection above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588272
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12588258
STACKED TRANSISTOR ISOLATION FEATURES AND METHODS OF FORMING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581690
METHOD OF FORMING SEMICONDUCTOR DEVICE WITH IMPLANTED NANOSHEETS
2y 5m to grant Granted Mar 17, 2026
Patent 12575170
LOW TEMPERATURE, HIGH GERMANIUM, HIGH BORON SIGE:B PEPI WITH A SILICON RICH CAPPING LAYER FOR ULTRA-LOW PMOS CONTACT RESISTIVITY AND THERMAL STABILITY
2y 5m to grant Granted Mar 10, 2026
Patent 12563732
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+4.8%)
3y 2m
Median Time to Grant
Low
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month